Binary To BCD Decoder
This device is a mechanism that converts a Binary value to its equivalent in Packed Binary Coded Decimal format. The device uses the Double Dabble algorithm to make the conversion.
Input arguments are evaluated to the nearest significant nibble; i.e. values 16 throught 255 (10 through FF hex) are all considered to be 2 nibble (8 bit) arguments. Period is 7680 generations per nibble, with the result residing in the nibbles immediately following the input argument. A marker is synced to the result.
From inception, this device was intended as a tailpiece for PM 2RING's Collatz Sequence Generator, which continually outputs numbers @p7680, ending in a repeating sequence of 4...2...1...4...2...1..., etc.

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Three major components: NIBBLER, REGISTER, and DABBLER; and three timing loops, along with support components form the mechanism as follows:
Binary data enters as p60 LWSSs from the left along the green path. Heisenburped down right, the gliders pass the initial value (via an inverter) to the left input of an adder. The LWSSs continue right into the NIBBLER, in blue at left. Two each p240 guns and a latch release a glider if any bit of a given nibble in the argument is present. The glider enters a ladder-like gauntlet of fanouts. Gliders from higher order nibbles will delete any and all gliders from lower order nibbles until eventually a single glider is released that is proportional to the length (in nibbles) of the current argument *240 generations. This signal is used to set the three timing loops as described below.
While the nibbler works, data enters the SHIFTING ADDER/REGISTER, shown in green, a root p1920 version of David Buckingham's adder. Arriving data is accepted into the register pre-shifted left by one bit. Output of the register is fanned out twice. The first fanout, in red, cycles data around to the right input of the adder at p1980. This effectively left shifts the data in the register back into the register with each pass. The next fanout, in green, sends data up right to output, and down right into the dabbler. The output data is fanned again; the resulting two streams are (initially) blocked by streams from a p30 gun into yet another fanout, shown in pink at right of the register.
The DABBLER, in orange at bottom, accepts output from the adder. Four each p240 LWSS guns reflect bits of nibbles down left through the logic. If the boolean:
bit8 OR ( bit4 AND (bit2 OR bit1))
is true, then the nibble has a value of 5 or greater, and one of two gap 4 reactions takes place in the collecting stabilized inverter. The resulting four gliders are tempered by a p30 gun, resulting in two gliders at p60 (the value three), which is cycled in sync to the left input of the adder with the adder's shifted output from the feedback loop.
The three timing loops, all stretched versions of the memory cell from Paul Rendell's Turing Machine, are, from left to right:
PROCESS END, NW to SE, in red at left,
PASS START, NW to SE, in yellow at center, and
PASS STOP, NE to SW, in violet at right.
The PROCESS END loop, at p1860, is set by one of the signals from the nibbler. With pass period of 1920, the glider in this loop cycles forward each pass until eventually, it kicks back the glider from an associated p1920 gun, erasing the glider in the loop. The kicked-back glider is reflected up left, and initiates the output/reset of the process which I'll describe below.
The PASS START and PASS STOP loops are also set by output of the nibbler. They release gliders that enable and disable the dabbler from processing nibbles. A latch (Paul Rendell's type A, as are all latches) at the top of the dabbler provides a glider stream blocking the 8bit and 4bit reflecting LWSSs, assuring a boolean FALSE result and thereby precluding output of the added three.
The START PASS loop at p1920 always starts dabbler action (by opening the latch) at the nibble immediately following the initial data. The STOP PASS loop, however, must take into account a growing number of nibbles as the data is not only left shifted, but three is added occasionally, and so the result will occasionally grow faster than one bit per pass. After MANY kneadings, tweaks, retiming and a complete change of orientation, I finally arrived at this working rendition.
Taking a page from construction arm technology, the mechanism in red, to the right of the STOP LOOP, places a boat in the up right glider path of that loop. The glider in the loop is reflected out and reenters the loop so as to be 240 generations delayed. A p7680 gun, in pink below the boat maker, provides the pulse that creates the boat. This same gun, via fanout, also creates a LWSS which will be used to erase the loop when the time is right.
When the PROCESS END loop fires, its output is fanned:
Up left is shown eaten, but is used to signal that the converter is ready to accept a new argument.
Up right converts to LWSS, in grey across the top, and provides two signals;
One, via heisenburp, 6 advancing guns and a number of reflectors, provides a LWSS that will react with the LWSS from the aforementioned p7680 gun. This collision creates two gliders, one up right, deleted by a p8 blocker, and one up left, where it cycles back and forth between two pentadecathlons at p60 in the glide path of the stop loop glider. When this glider arrives both are destroyed, erasing the loop. If the rightward LWSS is not present at the p7680 frame, the leftward LWSS is deleted by the third pentadecathlon in the cluster, all shown in grey.
The second glider, by inverter at top, and14 gun advancer sets a latch which provides a kickback stream in the downward glide path of the start pass loop. The kicked back start glider reflects around, morphs right as LWSS (in yellow) and sets the rest of the end process. Heisenburped down left, a latch (in pink) is set which delivers an inverting stream to the p30 gun creating the blocking streams to the output of the register. This opens the path for data in the register to be released, and a path for a copy of the output to be fed back and destroy the copy of the register's contents in the feedback loop of the register, thereby erasing it.
Lastly, the yellow path LWSS is converted to a glider up left which is fanned twice.
First, glider to LWSS left, in green, to reset the latch that kicks back the start pass glider,
Second, upwards to LWSS, in red at top, to create a marker synced to output data,
and lastly, glider around to reset the latch which opens the output blocker.

- BCDwDisplay.jpg (25.2 KiB) Viewed 29111 times
As zipped, the mechanism appears as above, except there are eight each seven-segment display modules.
From the bottom, in BLUE, PM 2RING's Collatz Sequence Generator. Above it in RED, an addendum that will put collatz processing on hold while the BCD module computes. Next in BLACK, the Binary to BCD converter.
For those interested, a lengthy description of the rest of the mechanism (all associated with display) is in a pair of .txt files in a ZIP, along with some jpgs for visual aid, which I am placing in the next post due to post size restrictions. For now the components, continuing counter-clockwise are:
In ORANGE, an 8 stage nibbler feeding in GREEN, a p240 to p960 converter.
Green data into RED, p60 to p30 converter turns packed BCD @p60 to unpacked BCD @p30. Data up into a 4 bit p240 to p960 converter, in VIOLET.
Signal out of the BCD, up right in violet, triggers the two p240 to p960 converters, starts a set/reset p960 gun, in RED at right center, and continues up to set the divert latches for each of the eight 7-segment modules.
Next, in BLUE, is a Binary to Ordinal module, then ordinal up to a segment encoder in YELLOW. Lastly, in PINK is one of the eight 7-segment modules, with its companion diverting/segment decoding mechanism at its lower right in GREY.
I preset the zipped mechanism with a starting value of 49,263. This yields a sequence of 221 terms before repeating, with a maximum value of 16,179,424.
This comes close to the 24 bit capacity of the BCD converter: 2^24-1=16,777,215.
It Hashes in Golly quite nicely @ 8^2,
Enjoy,
Mark Walsh (aka triller)