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We can also take Izhora, expand the RAM size, and compile the original Subleq code into Izhora's Subleq2 variant.

Inputs could possibly be handled via Lua/Python script that takes keyboard inputs and modifies the necessary cells, while stepping the simulation by a set 2^n amount a bunch of times ...

Seems to emulate a rule:

x = 33, y = 33, rule = Bliptile
C32A$A.A.A.A.A.A.A.A.A.A.A.A.A.A.A.A.A$33A$A.A.A.A.A.A.A.A.A.A.A.A.A.
A.A.A.A$33A$A.A.A.A.A.A.A.A.A.A.A.A.A.A.A.A.A$33A$A.A.A.A.A.A.A.A.A.A
.A.A.A.A.A.A.A$33A$A.A.A.A.A.A.A.A.A.A.A.A.A.A.A.A.A$33A$A.A.A.A.A.A.
A.A.A.A.A.A.A.A.A.A.A$33A$A.A ...

7 segment display but it counts

x = 197, y = 142, rule = Bliptile
118.3A6.2A.3A2.2A.A.A.3A.2A2.3A$120.A5.A3.A3.A3.3A.A3.A.A2.A$119.A2.
3A2.A2.2A2.A.A.A.A.2A2.A.A2.A$119.A8.A.A3.A.A.A.A.A3.A.A2.A$119.A6.2A
2.3A2.2A.A.A.3A.A.A2.A3$126.25A$122.3A.A.A.A.A.A.A.A.A.A.A.A.A.A.2A$
122.A.A.27A.3A$122.3A.A ...

might as well dump the smallest components i could build/find off the forums here

x = 239, y = 146, rule = Bliptile
19$26.A2.2A2.2A2.2A3.A2.3A30.A2.2A2.2A5.A.A2.A2.2A2.3A2.A2.2A2.3A2.2A
$25.A.A.A.A.A.A.A.A.A.A2.A30.A.A.A.A.A.A4.A.A.A.A.A.A2.A2.A.A.A.A2.A
2.A$25.3A.A.A.A.A.A.A.A.A2.A30.3A.A.A.A.A4 ...

p18 serial to parallel
can support higher periods by adjusting the delay at the top of each module
note that the fastest convenient serial signal is p10 but an xor gate recovers at p18

x = 315, y = 89, rule = Banks-IV
127.3C12.3C14.3C12.3C14.3C12.3C14.3C12.3C14.3C12.3C14.3C12.3C$127.C.C
12.C.C14.C ...

i built a p2 mod 64 delay circuit. (idk if that's the correct naming convention)
for short let's just call it the "micro delayer" to be consistent with the name i used in my first post.

the main giant body takes 5 bits of input + 1 signal and outputs that signal delayed by any even number of ticks ...

demultiplexer, 32x64 per tile, arranged for 3 bits and 8 addresses

x = 303, y = 240, rule = Banks-IV
33.3C14.3C12.3C14.3C12.3C14.3C12.3C14.3C12.3C14.3C12.3C14.3C12.3C14.
3C12.3C14.3C$33.C.C14.C.C12.C.C14.C.C12.C.C14.C.C12.C.C14.C.C12.C.C
14.C.C12.C.C14.C.C12.C.C14.C.C12.C.C14.C.C$31.3C.16C.3C8.3C ...

binary counters, set to p64, can theoretically be attached to a mod 64 delay circuit to make arbitrary delays for construction

x = 245, y = 161, rule = Banks-IV
24.C.C$24.C.C47.C.C45.C.C45.C.C45.C.C$24.CBC47.C.C45.C.C45.C.C45.C.C$
24.CAC47.C.C45.C.C45.C.C45.C.C$24.C.C47.C.C45.C.C45.C.C45.C.C$24.C ...

i tried running my script on this set of logic gates. it's 124x202. the resulting construction recipe was 11,852,032 cells long, which i won't be posting here. it's 19kb, and that's with .rle.gz encoding.
the longest replicator in Golly/Patterns is Codd/Goucher-replicator.mc.gz, which is 7,562,569 ...

still undecided whether i want to make a loop replicator or a proper jank-free version as originally intended...

anyway here's a script that generates a near-optimal recipe for any given binary pattern.
the RLE files are typically so large that it's more efficient to actually save it as a file ...

Edit: Could anyone tell me how they do the slow salvo stuff? I want to try to make things but i really can't find much from trial & error.


For the base mechanics, it's just these:

x = 40, y = 44, rule = Sticky
9.A13.A12.3A$8.A15.A11.A$7.5A9.5A10.2A$8.A15.A11.A$9.A13.A12.A3$8.CB
12.CB12.CB$A ...

So we've been making a FlipJump computer on the Discord

here's a 16-bit FlipJump CPU hooked up to 128 bits of RAM
the RAM has a builtin "read 32 bits" operation every 16 bits which is how it reads the next instruction
the program it's running is just a basic test: the first number is "22" and the ...

Proof of concept "Recipe Separator" device (based on the Sticky version above) which can separate a single loop recipe into 2 halves, if timed right:
x = 1106, y = 176, rule = Banks-IV
59.6C4.3C.3C$59.C.2C.C4.C.C.C.C$57.3C.2C.6C.3C.3C$57.C2.C2.C2.2C2.C3.
C2.3C3.3C$57.3C.2C.6C.3C.3C.C3.C.C$58.2C.2C ...

Okay so maybe the "clock" things in the previous image were incorrect. Banks needs timing freedom on both left and right sides of the arm if we want to construct anything meaningful, so there will probably have to be some decoder magic happening from a single channel construction loop instead ...

what do the labels Z, NZ, TDEC, INC refer to? Additionally, what are you going to use the circuit components for? I assume it is related to an "APGsembly compiler".

The components are referring to those found in this LifeWiki page: https://conwaylife.com/wiki/APGsembly
Just scroll down to see ...

I've come up with a bit of a rough method for constructing the right endpoint of the machine. This assumes that the child's left endpoint and most of the loop and child construction bar have already been built.

Phase 1 uses the main long upward construction bar (yellow) to build a sideways ...

apparently the shortest possible repeat time for a stream is 9, as you can use a signal merger to merge signals into the same lane 10 ticks apart then use another merger to speed up the last signal by 1 tick:
x = 59, y = 44, rule = Banks-IV
13.2C2.3C.C.C2.2C2.C2.2C2.C3.3C$13.C.C.C3.C.C.C3.C.C.C.C ...

ok so islptng and I have determined that it's possible to create a loop replicator. with these, the conditional delayer mechanisms won't be needed. though a pure tape based replicator might be interesting too.

how to attach parent to child (zoom right, i don't know how to set the default camera ...

Here's a Demux and a Delayer module made from a crossover+andnot+booster that goes up to +32 and should be easily extensible to other values:
x = 300, y = 243, rule = Banks-IV
130.2C2.3C.C.C.C.C.C.C$130.C.C.C3.3C.C.C.C.C$130.C.C.2C2.C.C.C.C2.C$
130.C.C.C3.C.C.C.C.C.C$130.2C2.3C.C.C2.2C.C.C8$93.C ...

So. I heard this rule is Turing Complete and capable of constructing anything that doesn't contain a tub.
That means it's capable of self replication, isn't it?

The goal? Linear propagator.
The challenge? This is the construction arm:
x = 1106, y = 47, rule = Banks-IV
1026.3C$1026.C.C$1027C.3C$55 ...

Loop replicator complete!
Speed: (22,26)c/6974
Sizes:
Predecessor Pattern (given below): 3429x36
Full child replicator: 1739x27
Body: 36x27
Loop (Wrapped): 1718x9
Loop (Unraveled): 6860 cells long

Predecessor Pattern:

x = 3429, y = 36, rule = BliptileExtCU
15.2A$.7A5.3A.5A$.A5.2A.3A2.2A3.A ...

And now, the ruletable come out: Rule:TernaryJvN60

linear propagator replication unit: 7 tape lanes, construct-while-reading O(n) but HashLife is definitely not fond of it
x = 89, y = 72, rule = TernaryJvN60
62.J6.2H$62.J6.2H$62.J.pHH3.2H$62.J.TpSIpS.2H$62.JG2HGH.2H$62.JHITpS
2.2H$62.J.pS2HI ...

I just wanna say good luck to whoever makes a compiler for this.
hand-placed pain

very funny for a 13 year old kid. 7 years later it's still a pain to work with.
here's a suboptimal script that hacks together the custom upwards extension and constructs things at a safe distance, not employing ...

A stable period-doubler in sticky, probably can be reduced:

Here's the smallest one I could find:
x = 39, y = 5, rule = Sticky
33.A$BC5.BC.BC5.BC.BC5.BC.BC6.A$33.A.A$38.A$37.A!

It's the core of a binary counter (found in the chip collection of the main post of this thread ):
x = 74, y = 162 ...