
9999: Output = Z  Instr=I1 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}  Instr=I1 NOP; regs={'R4': 0, 'R0': 1, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00000: Output = Z  Instr=I2 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}  Instr=I2 NOP; regs={'R4': 0, 'R0': 2, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00001: Output = Z  Instr=I3 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}  Instr=I3 NOP; regs={'R4': 0, 'R0': 3, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00002: Output = Z  Instr=I4 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}  Instr=I4 NOP; regs={'R4': 0, 'R0': 4, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00003: Output = Z  Instr=I5 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}  Instr=I5 NOP; regs={'R4': 0, 'R0': 5, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00004: Output = Z  Instr=I6 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}  Instr=I6 NOP; regs={'R4': 0, 'R0': 6, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00005: Output = Z  Instr=I7 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}  Instr=I7 NOP; regs={'R4': 0, 'R0': 7, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00006: Output = Z  Instr=I8 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}  Instr=I8 NOP; regs={'R4': 0, 'R0': 8, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00007: Output = Z  Instr=I9 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}  Instr=I9 NOP; regs={'R4': 0, 'R0': 9, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00008: Output = Z  Instr=I10 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}  Instr=I10 NOP; regs={'R4': 0, 'R0': 10, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00009: Output = Z  Instr=I11 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}  Instr=I11 NOP; regs={'R4': 0, 'R0': 11, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00010: Output = Z  Instr=I12 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}  Instr=I12 NOP; regs={'R4': 0, 'R0': 12, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00011: Output = Z  Instr=I13 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}  Instr=I13 NOP; regs={'R4': 0, 'R0': 13, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00012: Output = Z  Instr=I14 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}  Instr=I14 NOP; regs={'R4': 0, 'R0': 14, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00013: Output = Z  Instr=I15 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}  Instr=I15 NOP; regs={'R4': 0, 'R0': 15, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00014: Output = Z  Instr=I16 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}  Instr=I16 NOP; regs={'R4': 0, 'R0': 16, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00015: Output = Z  Instr=I17 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}  Instr=I17 NOP; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00016: Output = Z  Instr=I18 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}  Instr=I18 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00017: Output = Z  Instr=I19 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '0'], 'T1': [0, '0']}; mem={}
00018: Output = Z  Instr=I20 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [1, '00'], 'T1': [0, '0']}; mem={}
00019: Output = Z  Instr=I21 SET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [1, '0x'], 'T1': [0, '0']}; mem={}  Instr=I21 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [1, '01'], 'T1': [0, '0']}; mem={}
00020: Output = Z  Instr=I22 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [2, '010'], 'T1': [0, '0']}; mem={}
00021: Output = Z  Instr=I23 SET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [2, '01x'], 'T1': [0, '0']}; mem={}  Instr=I23 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [2, '011'], 'T1': [0, '0']}; mem={}
00022: Output = Z  Instr=I24 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [3, '0110'], 'T1': [0, '0']}; mem={}
00023: Output = Z  Instr=I25 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [4, '01100'], 'T1': [0, '0']}; mem={}
00024: Output = Z  Instr=I26 SET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [4, '0110x'], 'T1': [0, '0']}; mem={}  Instr=I26 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [4, '01101'], 'T1': [0, '0']}; mem={}
00025: Output = NZ  Instr=I26 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [3, '01101'], 'T1': [0, '0']}; mem={}
00026: Output = NZ  Instr=I26 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [2, '01101'], 'T1': [0, '0']}; mem={}
00027: Output = NZ  Instr=I26 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [1, '01101'], 'T1': [0, '0']}; mem={}
00028: Output = NZ  Instr=I26 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '0']}; mem={}
00029: Output = Z  Instr=I27 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '0']}; mem={}
00030: Output = Z  Instr=I28 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '0']}; mem={}
00031: Output = Z  Instr=I29 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [1, '00']}; mem={}
00032: Output = Z  Instr=I30 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [2, '000']}; mem={}
00033: Output = Z  Instr=I31 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [3, '0000']}; mem={}
00034: Output = Z  Instr=I32 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [4, '00000']}; mem={}
00035: Output = Z  Instr=I33 SET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [4, '0000x']}; mem={}  Instr=I33 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [4, '00001']}; mem={}
00036: Output = Z  Instr=I34 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [5, '000010']}; mem={}
00037: Output = Z  Instr=I35 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [6, '0000100']}; mem={}
00038: Output = Z  Instr=I36 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [7, '00001000']}; mem={}
00039: Output = Z  Instr=I37 SET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [7, '0000100x']}; mem={}  Instr=I37 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [7, '00001001']}; mem={}
00040: Output = Z  Instr=I38 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [8, '000010010']}; mem={}
00041: Output = Z  Instr=I39 SET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [8, '00001001x']}; mem={}  Instr=I39 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [8, '000010011']}; mem={}
00042: Output = NZ  Instr=I39 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [7, '000010011']}; mem={}
00043: Output = NZ  Instr=I39 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [6, '000010011']}; mem={}
00044: Output = NZ  Instr=I39 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [5, '000010011']}; mem={}
00045: Output = NZ  Instr=I39 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [4, '000010011']}; mem={}
00046: Output = NZ  Instr=I39 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [3, '000010011']}; mem={}
00047: Output = NZ  Instr=I39 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [2, '000010011']}; mem={}
00048: Output = NZ  Instr=I39 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [1, '000010011']}; mem={}
00049: Output = NZ  Instr=I39 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00050: Output = Z  Instr=I40 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00051: Output = Z  Instr=I41 OUTPUT 1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=I41 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00052: Output = Z  Instr=I42 OUTPUT .; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=I42 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00053: Output = Z  Instr=NXD OUTPUT 6; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=NXD NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00054: Output = Z  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00055: Output = NZ  Instr=A1 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00056: Output = NZ  Instr=A1 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00057: Output = NZ  Instr=A1 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00058: Output = NZ  Instr=A1 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00059: Output = NZ  Instr=A1 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00060: Output = NZ  Instr=A1 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00061: Output = NZ  Instr=A1 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00062: Output = NZ  Instr=A1 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00063: Output = NZ  Instr=A1 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00064: Output = NZ  Instr=A1 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00065: Output = NZ  Instr=A1 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00066: Output = NZ  Instr=A1 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00067: Output = NZ  Instr=A1 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00068: Output = NZ  Instr=A1 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00069: Output = NZ  Instr=A1 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00070: Output = NZ  Instr=A1 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00071: Output = NZ  Instr=A1 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00072: Output = NZ  Instr=A1 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A1 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00073: Output = Z  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00074: Output = NZ  Instr=A2 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00075: Output = NZ  Instr=A2 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00076: Output = NZ  Instr=A2 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00077: Output = NZ  Instr=A2 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00078: Output = NZ  Instr=A2 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00079: Output = NZ  Instr=A2 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00080: Output = NZ  Instr=A2 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00081: Output = NZ  Instr=A2 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00082: Output = NZ  Instr=A2 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00083: Output = NZ  Instr=A2 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00084: Output = NZ  Instr=A2 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00085: Output = NZ  Instr=A2 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00086: Output = NZ  Instr=A2 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00087: Output = NZ  Instr=A2 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00088: Output = NZ  Instr=A2 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00089: Output = NZ  Instr=A2 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00090: Output = NZ  Instr=A2 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00091: Output = NZ  Instr=A2 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}  Instr=A2 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00092: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00093: Output = NZ  Instr=A4 READ T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00094: Output = Z  Instr=A5 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 0, 'T4': [0, '0'], 'T2': [0, 'x'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00095: Output = Z  Instr=A6 RESET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 0, 'T4': [0, '0'], 'T2': [0, 'x'], 'T3': [0, '0'], 'T0': [0, 'x1101'], 'T1': [0, '000010011']}; mem={}  Instr=A6 MUL 0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 0, 'T4': [0, '0'], 'T2': [0, 'x'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011']}; mem={}
00096: Output = Z  Instr=A7 RESET T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 0, 'T4': [0, '0'], 'T2': [0, 'x'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A7 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [0, '01101'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00097: Output = NZ  Instr=A8 INC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0'], 'T3': [0, '0'], 'T0': [1, '01101'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00098: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 0, 'T4': [0, '0'], 'T2': [1, '00'], 'T3': [0, '0'], 'T0': [1, '01101'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00099: Output = NZ  Instr=A4 READ T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 0, 'T4': [0, '0'], 'T2': [1, '00'], 'T3': [0, '0'], 'T0': [1, '01101'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00100: Output = Z  Instr=A5 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 0, 'T4': [0, '0'], 'T2': [1, '0x'], 'T3': [0, '0'], 'T0': [1, '01101'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00101: Output = NZ  Instr=A6 SET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 0, 'T4': [0, '0'], 'T2': [1, '0x'], 'T3': [0, '0'], 'T0': [1, '0x101'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A6 MUL 1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 0, 'T4': [0, '0'], 'T2': [1, '0x'], 'T3': [0, '0'], 'T0': [1, '01101'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00102: Output = Z  Instr=A7 RESET T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 0, 'T4': [0, '0'], 'T2': [1, '0x'], 'T3': [0, '0'], 'T0': [1, '01101'], 'T1': [0, '000010011'], 'MUL': '00101'}; mem={}  Instr=A7 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 0, 'T4': [0, '0'], 'T2': [1, '00'], 'T3': [0, '0'], 'T0': [1, '01101'], 'T1': [0, '000010011'], 'MUL': '00101'}; mem={}
00103: Output = NZ  Instr=A8 INC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 0, 'T4': [0, '0'], 'T2': [1, '00'], 'T3': [0, '0'], 'T0': [2, '01101'], 'T1': [0, '000010011'], 'MUL': '00101'}; mem={}
00104: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 0, 'T4': [0, '0'], 'T2': [2, '000'], 'T3': [0, '0'], 'T0': [2, '01101'], 'T1': [0, '000010011'], 'MUL': '00101'}; mem={}
00105: Output = NZ  Instr=A4 READ T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 0, 'T4': [0, '0'], 'T2': [2, '000'], 'T3': [0, '0'], 'T0': [2, '01101'], 'T1': [0, '000010011'], 'MUL': '00101'}; mem={}
00106: Output = Z  Instr=A5 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 0, 'T4': [0, '0'], 'T2': [2, '00x'], 'T3': [0, '0'], 'T0': [2, '01101'], 'T1': [0, '000010011'], 'MUL': '00101'}; mem={}
00107: Output = NZ  Instr=A6 SET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 0, 'T4': [0, '0'], 'T2': [2, '00x'], 'T3': [0, '0'], 'T0': [2, '01x01'], 'T1': [0, '000010011'], 'MUL': '00101'}; mem={}  Instr=A6 MUL 1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 0, 'T4': [0, '0'], 'T2': [2, '00x'], 'T3': [0, '0'], 'T0': [2, '01101'], 'T1': [0, '000010011'], 'MUL': '00101'}; mem={}
00108: Output = NZ  Instr=A7 SET T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 0, 'T4': [0, '0'], 'T2': [2, '00x'], 'T3': [0, '0'], 'T0': [2, '01101'], 'T1': [0, '000010011'], 'MUL': '00111'}; mem={}  Instr=A7 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 0, 'T4': [0, '0'], 'T2': [2, '001'], 'T3': [0, '0'], 'T0': [2, '01101'], 'T1': [0, '000010011'], 'MUL': '00111'}; mem={}
00109: Output = NZ  Instr=A8 INC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 0, 'T4': [0, '0'], 'T2': [2, '001'], 'T3': [0, '0'], 'T0': [3, '01101'], 'T1': [0, '000010011'], 'MUL': '00111'}; mem={}
00110: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 0, 'T4': [0, '0'], 'T2': [3, '0010'], 'T3': [0, '0'], 'T0': [3, '01101'], 'T1': [0, '000010011'], 'MUL': '00111'}; mem={}
00111: Output = NZ  Instr=A4 READ T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 0, 'T4': [0, '0'], 'T2': [3, '0010'], 'T3': [0, '0'], 'T0': [3, '01101'], 'T1': [0, '000010011'], 'MUL': '00111'}; mem={}
00112: Output = Z  Instr=A5 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 0, 'T4': [0, '0'], 'T2': [3, '001x'], 'T3': [0, '0'], 'T0': [3, '01101'], 'T1': [0, '000010011'], 'MUL': '00111'}; mem={}
00113: Output = Z  Instr=A6 RESET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 0, 'T4': [0, '0'], 'T2': [3, '001x'], 'T3': [0, '0'], 'T0': [3, '011x1'], 'T1': [0, '000010011'], 'MUL': '00111'}; mem={}  Instr=A6 MUL 0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 0, 'T4': [0, '0'], 'T2': [3, '001x'], 'T3': [0, '0'], 'T0': [3, '01101'], 'T1': [0, '000010011'], 'MUL': '00111'}; mem={}
00114: Output = NZ  Instr=A7 SET T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 0, 'T4': [0, '0'], 'T2': [3, '001x'], 'T3': [0, '0'], 'T0': [3, '01101'], 'T1': [0, '000010011'], 'MUL': '00011'}; mem={}  Instr=A7 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 0, 'T4': [0, '0'], 'T2': [3, '0011'], 'T3': [0, '0'], 'T0': [3, '01101'], 'T1': [0, '000010011'], 'MUL': '00011'}; mem={}
00115: Output = NZ  Instr=A8 INC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 0, 'T4': [0, '0'], 'T2': [3, '0011'], 'T3': [0, '0'], 'T0': [4, '01101'], 'T1': [0, '000010011'], 'MUL': '00011'}; mem={}
00116: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 0, 'T4': [0, '0'], 'T2': [4, '00110'], 'T3': [0, '0'], 'T0': [4, '01101'], 'T1': [0, '000010011'], 'MUL': '00011'}; mem={}
00117: Output = NZ  Instr=A4 READ T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 0, 'T4': [0, '0'], 'T2': [4, '00110'], 'T3': [0, '0'], 'T0': [4, '01101'], 'T1': [0, '000010011'], 'MUL': '00011'}; mem={}
00118: Output = Z  Instr=A5 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 0, 'T4': [0, '0'], 'T2': [4, '0011x'], 'T3': [0, '0'], 'T0': [4, '01101'], 'T1': [0, '000010011'], 'MUL': '00011'}; mem={}
00119: Output = NZ  Instr=A6 SET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 0, 'T4': [0, '0'], 'T2': [4, '0011x'], 'T3': [0, '0'], 'T0': [4, '0110x'], 'T1': [0, '000010011'], 'MUL': '00011'}; mem={}  Instr=A6 MUL 1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 0, 'T4': [0, '0'], 'T2': [4, '0011x'], 'T3': [0, '0'], 'T0': [4, '01101'], 'T1': [0, '000010011'], 'MUL': '00011'}; mem={}
00120: Output = NZ  Instr=A7 SET T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 0, 'T4': [0, '0'], 'T2': [4, '0011x'], 'T3': [0, '0'], 'T0': [4, '01101'], 'T1': [0, '000010011'], 'MUL': '00110'}; mem={}  Instr=A7 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 0, 'T4': [0, '0'], 'T2': [4, '00111'], 'T3': [0, '0'], 'T0': [4, '01101'], 'T1': [0, '000010011'], 'MUL': '00110'}; mem={}
00121: Output = Z  Instr=A8 INC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 0, 'T4': [0, '0'], 'T2': [4, '00111'], 'T3': [0, '0'], 'T0': [5, '011010'], 'T1': [0, '000010011'], 'MUL': '00110'}; mem={}
00122: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 0, 'T4': [0, '0'], 'T2': [5, '001110'], 'T3': [0, '0'], 'T0': [5, '011010'], 'T1': [0, '000010011'], 'MUL': '00110'}; mem={}
00123: Output = NZ  Instr=A4 READ T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 0, 'T4': [0, '0'], 'T2': [5, '001110'], 'T3': [0, '0'], 'T0': [5, '011010'], 'T1': [0, '000010011'], 'MUL': '00110'}; mem={}
00124: Output = Z  Instr=A5 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 0, 'T4': [0, '0'], 'T2': [5, '00111x'], 'T3': [0, '0'], 'T0': [5, '011010'], 'T1': [0, '000010011'], 'MUL': '00110'}; mem={}
00125: Output = Z  Instr=A6 RESET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 0, 'T4': [0, '0'], 'T2': [5, '00111x'], 'T3': [0, '0'], 'T0': [5, '01101x'], 'T1': [0, '000010011'], 'MUL': '00110'}; mem={}  Instr=A6 MUL 0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 0, 'T4': [0, '0'], 'T2': [5, '00111x'], 'T3': [0, '0'], 'T0': [5, '011010'], 'T1': [0, '000010011'], 'MUL': '00110'}; mem={}
00126: Output = Z  Instr=A7 RESET T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 0, 'T4': [0, '0'], 'T2': [5, '00111x'], 'T3': [0, '0'], 'T0': [5, '011010'], 'T1': [0, '000010011'], 'MUL': '00011'}; mem={}  Instr=A7 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 0, 'T4': [0, '0'], 'T2': [5, '001110'], 'T3': [0, '0'], 'T0': [5, '011010'], 'T1': [0, '000010011'], 'MUL': '00011'}; mem={}
00127: Output = Z  Instr=A8 INC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 0, 'T4': [0, '0'], 'T2': [5, '001110'], 'T3': [0, '0'], 'T0': [6, '0110100'], 'T1': [0, '000010011'], 'MUL': '00011'}; mem={}
00128: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 0, 'T4': [0, '0'], 'T2': [6, '0011100'], 'T3': [0, '0'], 'T0': [6, '0110100'], 'T1': [0, '000010011'], 'MUL': '00011'}; mem={}
00129: Output = NZ  Instr=A4 READ T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 0, 'T4': [0, '0'], 'T2': [6, '0011100'], 'T3': [0, '0'], 'T0': [6, '0110100'], 'T1': [0, '000010011'], 'MUL': '00011'}; mem={}
00130: Output = Z  Instr=A5 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 0, 'T4': [0, '0'], 'T2': [6, '001110x'], 'T3': [0, '0'], 'T0': [6, '0110100'], 'T1': [0, '000010011'], 'MUL': '00011'}; mem={}
00131: Output = Z  Instr=A6 RESET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 0, 'T4': [0, '0'], 'T2': [6, '001110x'], 'T3': [0, '0'], 'T0': [6, '011010x'], 'T1': [0, '000010011'], 'MUL': '00011'}; mem={}  Instr=A6 MUL 0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 0, 'T4': [0, '0'], 'T2': [6, '001110x'], 'T3': [0, '0'], 'T0': [6, '0110100'], 'T1': [0, '000010011'], 'MUL': '00011'}; mem={}
00132: Output = NZ  Instr=A7 SET T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 0, 'T4': [0, '0'], 'T2': [6, '001110x'], 'T3': [0, '0'], 'T0': [6, '0110100'], 'T1': [0, '000010011'], 'MUL': '00001'}; mem={}  Instr=A7 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 0, 'T4': [0, '0'], 'T2': [6, '0011101'], 'T3': [0, '0'], 'T0': [6, '0110100'], 'T1': [0, '000010011'], 'MUL': '00001'}; mem={}
00133: Output = Z  Instr=A8 INC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 0, 'T4': [0, '0'], 'T2': [6, '0011101'], 'T3': [0, '0'], 'T0': [7, '01101000'], 'T1': [0, '000010011'], 'MUL': '00001'}; mem={}
00134: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 0, 'T4': [0, '0'], 'T2': [7, '00111010'], 'T3': [0, '0'], 'T0': [7, '01101000'], 'T1': [0, '000010011'], 'MUL': '00001'}; mem={}
00135: Output = NZ  Instr=A4 READ T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 0, 'T4': [0, '0'], 'T2': [7, '00111010'], 'T3': [0, '0'], 'T0': [7, '01101000'], 'T1': [0, '000010011'], 'MUL': '00001'}; mem={}
00136: Output = Z  Instr=A5 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 0, 'T4': [0, '0'], 'T2': [7, '0011101x'], 'T3': [0, '0'], 'T0': [7, '01101000'], 'T1': [0, '000010011'], 'MUL': '00001'}; mem={}
00137: Output = Z  Instr=A6 RESET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 0, 'T4': [0, '0'], 'T2': [7, '0011101x'], 'T3': [0, '0'], 'T0': [7, '0110100x'], 'T1': [0, '000010011'], 'MUL': '00001'}; mem={}  Instr=A6 MUL 0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 0, 'T4': [0, '0'], 'T2': [7, '0011101x'], 'T3': [0, '0'], 'T0': [7, '01101000'], 'T1': [0, '000010011'], 'MUL': '00001'}; mem={}
00138: Output = NZ  Instr=A7 SET T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 0, 'T4': [0, '0'], 'T2': [7, '0011101x'], 'T3': [0, '0'], 'T0': [7, '01101000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A7 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 0, 'T4': [0, '0'], 'T2': [7, '00111011'], 'T3': [0, '0'], 'T0': [7, '01101000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00139: Output = Z  Instr=A8 INC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 0, 'T4': [0, '0'], 'T2': [7, '00111011'], 'T3': [0, '0'], 'T0': [8, '011010000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00140: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 0, 'T4': [0, '0'], 'T2': [8, '001110110'], 'T3': [0, '0'], 'T0': [8, '011010000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00141: Output = NZ  Instr=A4 READ T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 0, 'T4': [0, '0'], 'T2': [8, '001110110'], 'T3': [0, '0'], 'T0': [8, '011010000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00142: Output = Z  Instr=A5 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 0, 'T4': [0, '0'], 'T2': [8, '00111011x'], 'T3': [0, '0'], 'T0': [8, '011010000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00143: Output = Z  Instr=A6 RESET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 0, 'T4': [0, '0'], 'T2': [8, '00111011x'], 'T3': [0, '0'], 'T0': [8, '01101000x'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A6 MUL 0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 0, 'T4': [0, '0'], 'T2': [8, '00111011x'], 'T3': [0, '0'], 'T0': [8, '011010000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00144: Output = Z  Instr=A7 RESET T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 0, 'T4': [0, '0'], 'T2': [8, '00111011x'], 'T3': [0, '0'], 'T0': [8, '011010000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A7 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 0, 'T4': [0, '0'], 'T2': [8, '001110110'], 'T3': [0, '0'], 'T0': [8, '011010000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00145: Output = Z  Instr=A8 INC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 0, 'T4': [0, '0'], 'T2': [8, '001110110'], 'T3': [0, '0'], 'T0': [9, '0110100000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00146: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 0, 'T4': [0, '0'], 'T2': [9, '0011101100'], 'T3': [0, '0'], 'T0': [9, '0110100000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00147: Output = NZ  Instr=A4 READ T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 0, 'T4': [0, '0'], 'T2': [9, '0011101100'], 'T3': [0, '0'], 'T0': [9, '0110100000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00148: Output = Z  Instr=A5 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 0, 'T4': [0, '0'], 'T2': [9, '001110110x'], 'T3': [0, '0'], 'T0': [9, '0110100000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00149: Output = Z  Instr=A6 RESET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 0, 'T4': [0, '0'], 'T2': [9, '001110110x'], 'T3': [0, '0'], 'T0': [9, '011010000x'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A6 MUL 0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 0, 'T4': [0, '0'], 'T2': [9, '001110110x'], 'T3': [0, '0'], 'T0': [9, '0110100000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00150: Output = Z  Instr=A7 RESET T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 0, 'T4': [0, '0'], 'T2': [9, '001110110x'], 'T3': [0, '0'], 'T0': [9, '0110100000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A7 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 0, 'T4': [0, '0'], 'T2': [9, '0011101100'], 'T3': [0, '0'], 'T0': [9, '0110100000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00151: Output = Z  Instr=A8 INC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 0, 'T4': [0, '0'], 'T2': [9, '0011101100'], 'T3': [0, '0'], 'T0': [10, '01101000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00152: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 0, 'T4': [0, '0'], 'T2': [10, '00111011000'], 'T3': [0, '0'], 'T0': [10, '01101000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00153: Output = NZ  Instr=A4 READ T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 0, 'T4': [0, '0'], 'T2': [10, '00111011000'], 'T3': [0, '0'], 'T0': [10, '01101000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00154: Output = Z  Instr=A5 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 0, 'T4': [0, '0'], 'T2': [10, '0011101100x'], 'T3': [0, '0'], 'T0': [10, '01101000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00155: Output = Z  Instr=A6 RESET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 0, 'T4': [0, '0'], 'T2': [10, '0011101100x'], 'T3': [0, '0'], 'T0': [10, '0110100000x'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A6 MUL 0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 0, 'T4': [0, '0'], 'T2': [10, '0011101100x'], 'T3': [0, '0'], 'T0': [10, '01101000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00156: Output = Z  Instr=A7 RESET T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 0, 'T4': [0, '0'], 'T2': [10, '0011101100x'], 'T3': [0, '0'], 'T0': [10, '01101000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A7 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 0, 'T4': [0, '0'], 'T2': [10, '00111011000'], 'T3': [0, '0'], 'T0': [10, '01101000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00157: Output = Z  Instr=A8 INC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 0, 'T4': [0, '0'], 'T2': [10, '00111011000'], 'T3': [0, '0'], 'T0': [11, '011010000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00158: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 0, 'T4': [0, '0'], 'T2': [11, '001110110000'], 'T3': [0, '0'], 'T0': [11, '011010000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00159: Output = NZ  Instr=A4 READ T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 0, 'T4': [0, '0'], 'T2': [11, '001110110000'], 'T3': [0, '0'], 'T0': [11, '011010000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00160: Output = Z  Instr=A5 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 0, 'T4': [0, '0'], 'T2': [11, '00111011000x'], 'T3': [0, '0'], 'T0': [11, '011010000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00161: Output = Z  Instr=A6 RESET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 0, 'T4': [0, '0'], 'T2': [11, '00111011000x'], 'T3': [0, '0'], 'T0': [11, '01101000000x'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A6 MUL 0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 0, 'T4': [0, '0'], 'T2': [11, '00111011000x'], 'T3': [0, '0'], 'T0': [11, '011010000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00162: Output = Z  Instr=A7 RESET T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 0, 'T4': [0, '0'], 'T2': [11, '00111011000x'], 'T3': [0, '0'], 'T0': [11, '011010000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A7 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 0, 'T4': [0, '0'], 'T2': [11, '001110110000'], 'T3': [0, '0'], 'T0': [11, '011010000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00163: Output = Z  Instr=A8 INC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 0, 'T4': [0, '0'], 'T2': [11, '001110110000'], 'T3': [0, '0'], 'T0': [12, '0110100000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00164: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 0, 'T4': [0, '0'], 'T2': [12, '0011101100000'], 'T3': [0, '0'], 'T0': [12, '0110100000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00165: Output = NZ  Instr=A4 READ T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 0, 'T4': [0, '0'], 'T2': [12, '0011101100000'], 'T3': [0, '0'], 'T0': [12, '0110100000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00166: Output = Z  Instr=A5 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 0, 'T4': [0, '0'], 'T2': [12, '001110110000x'], 'T3': [0, '0'], 'T0': [12, '0110100000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00167: Output = Z  Instr=A6 RESET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 0, 'T4': [0, '0'], 'T2': [12, '001110110000x'], 'T3': [0, '0'], 'T0': [12, '011010000000x'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A6 MUL 0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 0, 'T4': [0, '0'], 'T2': [12, '001110110000x'], 'T3': [0, '0'], 'T0': [12, '0110100000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00168: Output = Z  Instr=A7 RESET T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 0, 'T4': [0, '0'], 'T2': [12, '001110110000x'], 'T3': [0, '0'], 'T0': [12, '0110100000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A7 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 0, 'T4': [0, '0'], 'T2': [12, '0011101100000'], 'T3': [0, '0'], 'T0': [12, '0110100000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00169: Output = Z  Instr=A8 INC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 0, 'T4': [0, '0'], 'T2': [12, '0011101100000'], 'T3': [0, '0'], 'T0': [13, '01101000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00170: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 0, 'T4': [0, '0'], 'T2': [13, '00111011000000'], 'T3': [0, '0'], 'T0': [13, '01101000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00171: Output = NZ  Instr=A4 READ T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 0, 'T4': [0, '0'], 'T2': [13, '00111011000000'], 'T3': [0, '0'], 'T0': [13, '01101000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00172: Output = Z  Instr=A5 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 0, 'T4': [0, '0'], 'T2': [13, '0011101100000x'], 'T3': [0, '0'], 'T0': [13, '01101000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00173: Output = Z  Instr=A6 RESET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 0, 'T4': [0, '0'], 'T2': [13, '0011101100000x'], 'T3': [0, '0'], 'T0': [13, '0110100000000x'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A6 MUL 0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 0, 'T4': [0, '0'], 'T2': [13, '0011101100000x'], 'T3': [0, '0'], 'T0': [13, '01101000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00174: Output = Z  Instr=A7 RESET T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 0, 'T4': [0, '0'], 'T2': [13, '0011101100000x'], 'T3': [0, '0'], 'T0': [13, '01101000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A7 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 0, 'T4': [0, '0'], 'T2': [13, '00111011000000'], 'T3': [0, '0'], 'T0': [13, '01101000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00175: Output = Z  Instr=A8 INC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 0, 'T4': [0, '0'], 'T2': [13, '00111011000000'], 'T3': [0, '0'], 'T0': [14, '011010000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00176: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 0, 'T4': [0, '0'], 'T2': [14, '001110110000000'], 'T3': [0, '0'], 'T0': [14, '011010000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00177: Output = NZ  Instr=A4 READ T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 0, 'T4': [0, '0'], 'T2': [14, '001110110000000'], 'T3': [0, '0'], 'T0': [14, '011010000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00178: Output = Z  Instr=A5 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 0, 'T4': [0, '0'], 'T2': [14, '00111011000000x'], 'T3': [0, '0'], 'T0': [14, '011010000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00179: Output = Z  Instr=A6 RESET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 0, 'T4': [0, '0'], 'T2': [14, '00111011000000x'], 'T3': [0, '0'], 'T0': [14, '01101000000000x'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A6 MUL 0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 0, 'T4': [0, '0'], 'T2': [14, '00111011000000x'], 'T3': [0, '0'], 'T0': [14, '011010000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00180: Output = Z  Instr=A7 RESET T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 0, 'T4': [0, '0'], 'T2': [14, '00111011000000x'], 'T3': [0, '0'], 'T0': [14, '011010000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A7 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 0, 'T4': [0, '0'], 'T2': [14, '001110110000000'], 'T3': [0, '0'], 'T0': [14, '011010000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00181: Output = Z  Instr=A8 INC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 0, 'T4': [0, '0'], 'T2': [14, '001110110000000'], 'T3': [0, '0'], 'T0': [15, '0110100000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00182: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 0, 'T4': [0, '0'], 'T2': [15, '0011101100000000'], 'T3': [0, '0'], 'T0': [15, '0110100000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00183: Output = NZ  Instr=A4 READ T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 0, 'T4': [0, '0'], 'T2': [15, '0011101100000000'], 'T3': [0, '0'], 'T0': [15, '0110100000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00184: Output = Z  Instr=A5 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 0, 'T4': [0, '0'], 'T2': [15, '001110110000000x'], 'T3': [0, '0'], 'T0': [15, '0110100000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00185: Output = Z  Instr=A6 RESET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 0, 'T4': [0, '0'], 'T2': [15, '001110110000000x'], 'T3': [0, '0'], 'T0': [15, '011010000000000x'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A6 MUL 0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 0, 'T4': [0, '0'], 'T2': [15, '001110110000000x'], 'T3': [0, '0'], 'T0': [15, '0110100000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00186: Output = Z  Instr=A7 RESET T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 0, 'T4': [0, '0'], 'T2': [15, '001110110000000x'], 'T3': [0, '0'], 'T0': [15, '0110100000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A7 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 0, 'T4': [0, '0'], 'T2': [15, '0011101100000000'], 'T3': [0, '0'], 'T0': [15, '0110100000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00187: Output = Z  Instr=A8 INC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 0, 'T4': [0, '0'], 'T2': [15, '0011101100000000'], 'T3': [0, '0'], 'T0': [16, '01101000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00188: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 0, 'T4': [0, '0'], 'T2': [16, '00111011000000000'], 'T3': [0, '0'], 'T0': [16, '01101000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00189: Output = NZ  Instr=A4 READ T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 0, 'T4': [0, '0'], 'T2': [16, '00111011000000000'], 'T3': [0, '0'], 'T0': [16, '01101000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00190: Output = Z  Instr=A5 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 0, 'T4': [0, '0'], 'T2': [16, '0011101100000000x'], 'T3': [0, '0'], 'T0': [16, '01101000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00191: Output = Z  Instr=A6 RESET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 0, 'T4': [0, '0'], 'T2': [16, '0011101100000000x'], 'T3': [0, '0'], 'T0': [16, '0110100000000000x'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A6 MUL 0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 0, 'T4': [0, '0'], 'T2': [16, '0011101100000000x'], 'T3': [0, '0'], 'T0': [16, '01101000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00192: Output = Z  Instr=A7 RESET T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 0, 'T4': [0, '0'], 'T2': [16, '0011101100000000x'], 'T3': [0, '0'], 'T0': [16, '01101000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A7 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 0, 'T4': [0, '0'], 'T2': [16, '00111011000000000'], 'T3': [0, '0'], 'T0': [16, '01101000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00193: Output = Z  Instr=A8 INC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 0, 'T4': [0, '0'], 'T2': [16, '00111011000000000'], 'T3': [0, '0'], 'T0': [17, '011010000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00194: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 0, 'T4': [0, '0'], 'T2': [17, '001110110000000000'], 'T3': [0, '0'], 'T0': [17, '011010000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00195: Output = NZ  Instr=A4 READ T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [17, '001110110000000000'], 'T3': [0, '0'], 'T0': [17, '011010000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00196: Output = Z  Instr=A5 READ T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [17, '00111011000000000x'], 'T3': [0, '0'], 'T0': [17, '011010000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00197: Output = Z  Instr=A6 RESET T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [17, '00111011000000000x'], 'T3': [0, '0'], 'T0': [17, '01101000000000000x'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A6 MUL 0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [17, '00111011000000000x'], 'T3': [0, '0'], 'T0': [17, '011010000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00198: Output = Z  Instr=A7 RESET T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [17, '00111011000000000x'], 'T3': [0, '0'], 'T0': [17, '011010000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A7 INC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [17, '001110110000000000'], 'T3': [0, '0'], 'T0': [17, '011010000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00199: Output = Z  Instr=A8 INC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [17, '001110110000000000'], 'T3': [0, '0'], 'T0': [18, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00200: Output = Z  Instr=A3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [18, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00201: Output = Z  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [18, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00202: Output = NZ  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [17, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00203: Output = NZ  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [16, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00204: Output = NZ  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [15, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00205: Output = NZ  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [14, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00206: Output = NZ  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [13, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00207: Output = NZ  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [12, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00208: Output = NZ  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [11, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00209: Output = NZ  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [10, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00210: Output = NZ  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [9, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00211: Output = NZ  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [8, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00212: Output = NZ  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [7, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00213: Output = NZ  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [6, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00214: Output = NZ  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [5, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00215: Output = NZ  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [4, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00216: Output = NZ  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [3, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00217: Output = NZ  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [2, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00218: Output = NZ  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [1, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00219: Output = NZ  Instr=A9 DEC T0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00220: Output = Z  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [18, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00221: Output = NZ  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [17, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00222: Output = NZ  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [16, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00223: Output = NZ  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [15, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00224: Output = NZ  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [14, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00225: Output = NZ  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [13, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00226: Output = NZ  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [12, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00227: Output = NZ  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [11, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00228: Output = NZ  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [10, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00229: Output = NZ  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [9, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00230: Output = NZ  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [8, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00231: Output = NZ  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [7, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00232: Output = NZ  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [6, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00233: Output = NZ  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [5, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00234: Output = NZ  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [4, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00235: Output = NZ  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [3, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00236: Output = NZ  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [2, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00237: Output = NZ  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [1, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00238: Output = NZ  Instr=A10 DEC T2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00239: Output = Z  Instr=A11 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A11 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00240: Output = Z  Instr=A12 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A12 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00241: Output = Z  Instr=A13 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A13 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00242: Output = Z  Instr=A14 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A14 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00243: Output = Z  Instr=A15 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A15 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00244: Output = Z  Instr=A16 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A16 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00245: Output = Z  Instr=A17 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A17 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00246: Output = Z  Instr=A18 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=A18 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00247: Output = Z  Instr=EVL INC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=EVL NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00248: Output = Z  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00249: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00250: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00251: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00252: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00253: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00254: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00255: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00256: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00257: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00258: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00259: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00260: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00261: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00262: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00263: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00264: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00265: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00266: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00267: Output = Z  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00268: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00269: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00270: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00271: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00272: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00273: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00274: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00275: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00276: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00277: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00278: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00279: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00280: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00281: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00282: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00283: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00284: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00285: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00286: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00287: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00288: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00289: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00290: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00291: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00292: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00293: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00294: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '00x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00295: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00296: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00297: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00298: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00299: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00300: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00301: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00302: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00303: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '00000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00304: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00305: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00306: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00307: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '00000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00308: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '00000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00309: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '00000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00310: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00311: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00312: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '00000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00313: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00314: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00315: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '000000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00316: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00317: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00318: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0000000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00319: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00320: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00321: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '00000000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00322: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00323: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00324: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '000000000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00325: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00326: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00327: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0000000000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00328: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00329: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00330: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '00000000000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00331: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00332: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00333: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '000000000000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00334: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00335: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00336: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0000000000000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00337: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00338: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00339: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '00000000000000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00340: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00341: Output = Z  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00342: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00343: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00344: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00345: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00346: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00347: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00348: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00349: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00350: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [9, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00351: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [8, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00352: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [7, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00353: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [6, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00354: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [5, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00355: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [4, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00356: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [3, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00357: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00358: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00359: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00360: Output = Z  Instr=B5 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00361: Output = Z  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00362: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00363: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00364: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00365: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00366: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00367: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00368: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00369: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 8, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00370: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 8, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 9, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00371: Output = Z  Instr=B7 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 9, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00372: Output = NZ  Instr=B7 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 8, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 0, 'R0': 18, 'R1': 8, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 8, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00373: Output = NZ  Instr=B7 INC R3; regs={'R4': 1, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 1, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00374: Output = NZ  Instr=B7 INC R3; regs={'R4': 2, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 2, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00375: Output = NZ  Instr=B7 INC R3; regs={'R4': 3, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 3, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 4, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00376: Output = NZ  Instr=B7 INC R3; regs={'R4': 4, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 4, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 5, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00377: Output = NZ  Instr=B7 INC R3; regs={'R4': 5, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 5, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 6, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00378: Output = NZ  Instr=B7 INC R3; regs={'R4': 6, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 6, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 7, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00379: Output = NZ  Instr=B7 INC R3; regs={'R4': 7, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 7, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 8, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00380: Output = NZ  Instr=B7 INC R3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00381: Output = Z  Instr=B8 NOP; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00382: Output = Z  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00383: Output = NZ  Instr=B9 INC R1; regs={'R4': 9, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00384: Output = NZ  Instr=B9 INC R1; regs={'R4': 9, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00385: Output = NZ  Instr=B9 INC R1; regs={'R4': 9, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00386: Output = NZ  Instr=B9 INC R1; regs={'R4': 9, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00387: Output = NZ  Instr=B9 INC R1; regs={'R4': 9, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00388: Output = NZ  Instr=B9 INC R1; regs={'R4': 9, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00389: Output = NZ  Instr=B9 INC R1; regs={'R4': 9, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00390: Output = NZ  Instr=B9 INC R1; regs={'R4': 9, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00391: Output = NZ  Instr=B9 INC R1; regs={'R4': 9, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00392: Output = NZ  Instr=B9 INC R1; regs={'R4': 9, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00393: Output = NZ  Instr=B9 INC R1; regs={'R4': 9, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00394: Output = NZ  Instr=B9 INC R1; regs={'R4': 9, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00395: Output = NZ  Instr=B9 INC R1; regs={'R4': 9, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00396: Output = NZ  Instr=B9 INC R1; regs={'R4': 9, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00397: Output = NZ  Instr=B9 INC R1; regs={'R4': 9, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00398: Output = NZ  Instr=B9 INC R1; regs={'R4': 9, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00399: Output = NZ  Instr=B9 INC R1; regs={'R4': 9, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00400: Output = NZ  Instr=B9 INC R1; regs={'R4': 9, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 9, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00401: Output = Z  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00402: Output = NZ  Instr=B10 INC R0; regs={'R4': 9, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 9, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00403: Output = NZ  Instr=B10 INC R0; regs={'R4': 9, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 9, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00404: Output = NZ  Instr=B10 INC R0; regs={'R4': 9, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 9, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00405: Output = NZ  Instr=B10 INC R0; regs={'R4': 9, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 9, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00406: Output = NZ  Instr=B10 INC R0; regs={'R4': 9, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 9, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00407: Output = NZ  Instr=B10 INC R0; regs={'R4': 9, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 9, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00408: Output = NZ  Instr=B10 INC R0; regs={'R4': 9, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 9, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00409: Output = NZ  Instr=B10 INC R0; regs={'R4': 9, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 9, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00410: Output = NZ  Instr=B10 INC R0; regs={'R4': 9, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 9, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00411: Output = NZ  Instr=B10 INC R0; regs={'R4': 9, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 9, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00412: Output = NZ  Instr=B10 INC R0; regs={'R4': 9, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 9, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00413: Output = NZ  Instr=B10 INC R0; regs={'R4': 9, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 9, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00414: Output = NZ  Instr=B10 INC R0; regs={'R4': 9, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 9, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00415: Output = NZ  Instr=B10 INC R0; regs={'R4': 9, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 9, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00416: Output = NZ  Instr=B10 INC R0; regs={'R4': 9, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 9, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00417: Output = NZ  Instr=B10 INC R0; regs={'R4': 9, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 9, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00418: Output = NZ  Instr=B10 INC R0; regs={'R4': 9, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 9, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00419: Output = NZ  Instr=B10 INC R0; regs={'R4': 9, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00420: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00421: Output = NZ  Instr=B12 READ T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00422: Output = Z  Instr=B13 READ T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00423: Output = Z  Instr=B14 RESET T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, 'x011101100000000000'], 'T3': [0, 'x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00424: Output = NZ  Instr=B15 INC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [0, '0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00425: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00426: Output = NZ  Instr=B12 READ T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00427: Output = Z  Instr=B13 READ T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00428: Output = Z  Instr=B14 RESET T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [1, '0x11101100000000000'], 'T3': [1, '0x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00429: Output = NZ  Instr=B15 INC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [1, '00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00430: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00431: Output = NZ  Instr=B12 READ T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00432: Output = Z  Instr=B13 READ T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '00x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00433: Output = NZ  Instr=B14 SET T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [2, '00x1101100000000000'], 'T3': [2, '00x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '00x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '001'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00434: Output = NZ  Instr=B15 INC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [2, '001'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00435: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0010'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00436: Output = NZ  Instr=B12 READ T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0010'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00437: Output = Z  Instr=B13 READ T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '001x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00438: Output = NZ  Instr=B14 SET T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [3, '001x101100000000000'], 'T3': [3, '001x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '001x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0011'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00439: Output = NZ  Instr=B15 INC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [3, '0011'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00440: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '00110'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00441: Output = NZ  Instr=B12 READ T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '00110'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00442: Output = Z  Instr=B13 READ T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00443: Output = NZ  Instr=B14 SET T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011x01100000000000'], 'T3': [4, '0011x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '00111'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00444: Output = NZ  Instr=B15 INC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [4, '00111'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00445: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '001110'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00446: Output = NZ  Instr=B12 READ T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '001110'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00447: Output = Z  Instr=B13 READ T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '00111x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00448: Output = Z  Instr=B14 RESET T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [5, '00111x1100000000000'], 'T3': [5, '00111x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '00111x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '001110'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00449: Output = NZ  Instr=B15 INC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [5, '001110'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00450: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011100'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00451: Output = NZ  Instr=B12 READ T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011100'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00452: Output = Z  Instr=B13 READ T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '001110x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00453: Output = NZ  Instr=B14 SET T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [6, '001110x100000000000'], 'T3': [6, '001110x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '001110x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00454: Output = NZ  Instr=B15 INC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [6, '0011101'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00455: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '00111010'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00456: Output = NZ  Instr=B12 READ T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '00111010'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00457: Output = Z  Instr=B13 READ T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00458: Output = NZ  Instr=B14 SET T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101x00000000000'], 'T3': [7, '0011101x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '00111011'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00459: Output = NZ  Instr=B15 INC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [7, '00111011'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00460: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '001110110'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00461: Output = NZ  Instr=B12 READ T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '001110110'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00462: Output = Z  Instr=B13 READ T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '00111011x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00463: Output = Z  Instr=B14 RESET T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [8, '00111011x0000000000'], 'T3': [8, '00111011x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '00111011x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '001110110'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00464: Output = NZ  Instr=B15 INC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [8, '001110110'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00465: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00466: Output = NZ  Instr=B12 READ T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00467: Output = Z  Instr=B13 READ T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '001110110x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00468: Output = Z  Instr=B14 RESET T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [9, '001110110x000000000'], 'T3': [9, '001110110x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '001110110x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00469: Output = NZ  Instr=B15 INC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [9, '0011101100'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00470: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '00111011000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00471: Output = NZ  Instr=B12 READ T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '00111011000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00472: Output = Z  Instr=B13 READ T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00473: Output = Z  Instr=B14 RESET T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100x00000000'], 'T3': [10, '0011101100x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '00111011000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00474: Output = NZ  Instr=B15 INC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [10, '00111011000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00475: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '001110110000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00476: Output = NZ  Instr=B12 READ T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '001110110000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00477: Output = Z  Instr=B13 READ T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '00111011000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00478: Output = Z  Instr=B14 RESET T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [11, '00111011000x0000000'], 'T3': [11, '00111011000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '00111011000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '001110110000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00479: Output = NZ  Instr=B15 INC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [11, '001110110000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00480: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00481: Output = NZ  Instr=B12 READ T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00482: Output = Z  Instr=B13 READ T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '001110110000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00483: Output = Z  Instr=B14 RESET T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [12, '001110110000x000000'], 'T3': [12, '001110110000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '001110110000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00484: Output = NZ  Instr=B15 INC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [12, '0011101100000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00485: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '00111011000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00486: Output = NZ  Instr=B12 READ T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '00111011000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00487: Output = Z  Instr=B13 READ T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00488: Output = Z  Instr=B14 RESET T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000x00000'], 'T3': [13, '0011101100000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '00111011000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00489: Output = NZ  Instr=B15 INC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [13, '00111011000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00490: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '001110110000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00491: Output = NZ  Instr=B12 READ T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '001110110000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00492: Output = Z  Instr=B13 READ T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '00111011000000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00493: Output = Z  Instr=B14 RESET T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [14, '00111011000000x0000'], 'T3': [14, '00111011000000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '00111011000000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '001110110000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00494: Output = NZ  Instr=B15 INC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [14, '001110110000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00495: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00496: Output = NZ  Instr=B12 READ T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00497: Output = Z  Instr=B13 READ T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '001110110000000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00498: Output = Z  Instr=B14 RESET T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [15, '001110110000000x000'], 'T3': [15, '001110110000000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '001110110000000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00499: Output = NZ  Instr=B15 INC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [15, '0011101100000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00500: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '00111011000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00501: Output = NZ  Instr=B12 READ T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '00111011000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00502: Output = Z  Instr=B13 READ T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00503: Output = Z  Instr=B14 RESET T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000x00'], 'T3': [16, '0011101100000000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '00111011000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00504: Output = NZ  Instr=B15 INC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [16, '00111011000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00505: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '001110110000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00506: Output = NZ  Instr=B12 READ T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '001110110000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00507: Output = Z  Instr=B13 READ T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '00111011000000000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00508: Output = Z  Instr=B14 RESET T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [17, '00111011000000000x0'], 'T3': [17, '00111011000000000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '00111011000000000x'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '001110110000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00509: Output = NZ  Instr=B15 INC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [17, '001110110000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00510: Output = Z  Instr=B11 TDEC R2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00511: Output = Z  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00512: Output = NZ  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00513: Output = NZ  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00514: Output = NZ  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00515: Output = NZ  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00516: Output = NZ  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00517: Output = NZ  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00518: Output = NZ  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00519: Output = NZ  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00520: Output = NZ  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00521: Output = NZ  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00522: Output = NZ  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00523: Output = NZ  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00524: Output = NZ  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00525: Output = NZ  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00526: Output = NZ  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00527: Output = NZ  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00528: Output = NZ  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00529: Output = NZ  Instr=B16 DEC T2; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00530: Output = Z  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00531: Output = NZ  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00532: Output = NZ  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00533: Output = NZ  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00534: Output = NZ  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00535: Output = NZ  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00536: Output = NZ  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00537: Output = NZ  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00538: Output = NZ  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00539: Output = NZ  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00540: Output = NZ  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00541: Output = NZ  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00542: Output = NZ  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00543: Output = NZ  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00544: Output = NZ  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00545: Output = NZ  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00546: Output = NZ  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00547: Output = NZ  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00548: Output = NZ  Instr=B17 DEC T3; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00549: Output = Z  Instr=ADD NOP; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00550: Output = Z  Instr=C1 TDEC R4; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00551: Output = NZ  Instr=C2 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00552: Output = Z  Instr=C4 SET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00553: Output = Z  Instr=C1 TDEC R4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00554: Output = NZ  Instr=C2 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00555: Output = NZ  Instr=C3 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00556: Output = NZ  Instr=C2 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00557: Output = Z  Instr=C4 SET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00558: Output = NZ  Instr=C4 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00559: Output = Z  Instr=C1 TDEC R4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00560: Output = NZ  Instr=C2 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00561: Output = Z  Instr=C4 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00562: Output = Z  Instr=C1 TDEC R4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00563: Output = NZ  Instr=C2 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00564: Output = NZ  Instr=C3 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00565: Output = NZ  Instr=C2 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00566: Output = NZ  Instr=C3 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00567: Output = NZ  Instr=C2 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00568: Output = NZ  Instr=C3 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x1101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0001101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00569: Output = NZ  Instr=C2 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0001101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00570: Output = NZ  Instr=C3 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '000x101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00571: Output = NZ  Instr=C2 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00572: Output = NZ  Instr=C3 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000x01100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000001100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00573: Output = NZ  Instr=C2 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000001100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00574: Output = Z  Instr=C4 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '00000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00575: Output = NZ  Instr=C4 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00576: Output = NZ  Instr=C4 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00577: Output = NZ  Instr=C4 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00578: Output = NZ  Instr=C4 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00579: Output = NZ  Instr=C4 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00580: Output = Z  Instr=C1 TDEC R4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00581: Output = NZ  Instr=C2 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00582: Output = Z  Instr=C4 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00583: Output = Z  Instr=C1 TDEC R4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00584: Output = NZ  Instr=C2 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00585: Output = NZ  Instr=C3 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00586: Output = NZ  Instr=C2 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00587: Output = Z  Instr=C4 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00588: Output = NZ  Instr=C4 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00589: Output = Z  Instr=C1 TDEC R4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00590: Output = NZ  Instr=C2 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00591: Output = Z  Instr=C4 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00592: Output = Z  Instr=C1 TDEC R4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00593: Output = NZ  Instr=C2 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00594: Output = NZ  Instr=C3 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00595: Output = NZ  Instr=C2 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00596: Output = NZ  Instr=C3 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00597: Output = NZ  Instr=C2 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00598: Output = Z  Instr=C4 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00599: Output = NZ  Instr=C4 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00600: Output = NZ  Instr=C4 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00601: Output = Z  Instr=C1 TDEC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00602: Output = NZ  Instr=C2 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00603: Output = Z  Instr=C4 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00604: Output = Z  Instr=C1 TDEC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00605: Output = Z  Instr=C5 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00606: Output = Z  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00607: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00608: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00609: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00610: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00611: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00612: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00613: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00614: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 8, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00615: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 8, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 9, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00616: Output = Z  Instr=C7 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 9, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00617: Output = NZ  Instr=C7 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 8, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 0, 'R0': 18, 'R1': 8, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 8, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00618: Output = NZ  Instr=C7 INC R3; regs={'R4': 1, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 1, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00619: Output = NZ  Instr=C7 INC R3; regs={'R4': 2, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 2, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00620: Output = NZ  Instr=C7 INC R3; regs={'R4': 3, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 3, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 4, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00621: Output = NZ  Instr=C7 INC R3; regs={'R4': 4, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 4, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 5, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00622: Output = NZ  Instr=C7 INC R3; regs={'R4': 5, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 5, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 6, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00623: Output = NZ  Instr=C7 INC R3; regs={'R4': 6, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 6, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 7, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00624: Output = NZ  Instr=C7 INC R3; regs={'R4': 7, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 7, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 8, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00625: Output = NZ  Instr=C7 INC R3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00626: Output = Z  Instr=MUL NOP; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00627: Output = Z  Instr=D1 TDEC R4; regs={'R4': 9, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00628: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00629: Output = NZ  Instr=D2 INC R1; regs={'R4': 8, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00630: Output = NZ  Instr=D2 INC R1; regs={'R4': 8, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00631: Output = NZ  Instr=D2 INC R1; regs={'R4': 8, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00632: Output = NZ  Instr=D2 INC R1; regs={'R4': 8, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00633: Output = NZ  Instr=D2 INC R1; regs={'R4': 8, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00634: Output = NZ  Instr=D2 INC R1; regs={'R4': 8, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00635: Output = NZ  Instr=D2 INC R1; regs={'R4': 8, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00636: Output = NZ  Instr=D2 INC R1; regs={'R4': 8, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00637: Output = NZ  Instr=D2 INC R1; regs={'R4': 8, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00638: Output = NZ  Instr=D2 INC R1; regs={'R4': 8, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00639: Output = NZ  Instr=D2 INC R1; regs={'R4': 8, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00640: Output = NZ  Instr=D2 INC R1; regs={'R4': 8, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00641: Output = NZ  Instr=D2 INC R1; regs={'R4': 8, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00642: Output = NZ  Instr=D2 INC R1; regs={'R4': 8, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00643: Output = NZ  Instr=D2 INC R1; regs={'R4': 8, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00644: Output = NZ  Instr=D2 INC R1; regs={'R4': 8, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00645: Output = NZ  Instr=D2 INC R1; regs={'R4': 8, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00646: Output = NZ  Instr=D2 INC R1; regs={'R4': 8, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 8, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00647: Output = Z  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00648: Output = NZ  Instr=D3 INC R0; regs={'R4': 8, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 8, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00649: Output = NZ  Instr=D3 INC R0; regs={'R4': 8, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 8, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00650: Output = NZ  Instr=D3 INC R0; regs={'R4': 8, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 8, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00651: Output = NZ  Instr=D3 INC R0; regs={'R4': 8, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 8, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00652: Output = NZ  Instr=D3 INC R0; regs={'R4': 8, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 8, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00653: Output = NZ  Instr=D3 INC R0; regs={'R4': 8, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 8, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00654: Output = NZ  Instr=D3 INC R0; regs={'R4': 8, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 8, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00655: Output = NZ  Instr=D3 INC R0; regs={'R4': 8, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 8, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00656: Output = NZ  Instr=D3 INC R0; regs={'R4': 8, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 8, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00657: Output = NZ  Instr=D3 INC R0; regs={'R4': 8, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 8, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00658: Output = NZ  Instr=D3 INC R0; regs={'R4': 8, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 8, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00659: Output = NZ  Instr=D3 INC R0; regs={'R4': 8, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 8, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00660: Output = NZ  Instr=D3 INC R0; regs={'R4': 8, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 8, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00661: Output = NZ  Instr=D3 INC R0; regs={'R4': 8, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 8, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00662: Output = NZ  Instr=D3 INC R0; regs={'R4': 8, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 8, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00663: Output = NZ  Instr=D3 INC R0; regs={'R4': 8, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 8, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00664: Output = NZ  Instr=D3 INC R0; regs={'R4': 8, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 8, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00665: Output = NZ  Instr=D3 INC R0; regs={'R4': 8, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00666: Output = Z  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00667: Output = NZ  Instr=D5 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}
00668: Output = NZ  Instr=D6 SET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
00669: Output = Z  Instr=D7 ADD B1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
00670: Output = NZ  Instr=D8 SET T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00671: Output = NZ  Instr=D8A INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00672: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00673: Output = NZ  Instr=D5 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00674: Output = Z  Instr=D6 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00675: Output = Z  Instr=D7 ADD B1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1x00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00676: Output = Z  Instr=D8 RESET T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1x00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00677: Output = NZ  Instr=D8A INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00678: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00679: Output = NZ  Instr=D5 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00680: Output = NZ  Instr=D6 SET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '10x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
00681: Output = Z  Instr=D7 ADD B1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '10x0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
00682: Output = NZ  Instr=D8 SET T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '10x0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00683: Output = NZ  Instr=D8A INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00684: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00685: Output = NZ  Instr=D5 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00686: Output = Z  Instr=D6 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '101x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00687: Output = Z  Instr=D7 ADD B1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '101x000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00688: Output = Z  Instr=D8 RESET T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '101x000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00689: Output = NZ  Instr=D8A INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00690: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00691: Output = NZ  Instr=D5 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00692: Output = Z  Instr=D6 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00693: Output = Z  Instr=D7 ADD B1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1010x00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00694: Output = Z  Instr=D8 RESET T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1010x00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00695: Output = NZ  Instr=D8A INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00696: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00697: Output = NZ  Instr=D5 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00698: Output = NZ  Instr=D6 SET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '10100x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
00699: Output = Z  Instr=D7 ADD B1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '10100x0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
00700: Output = NZ  Instr=D8 SET T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '10100x0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1010010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00701: Output = NZ  Instr=D8A INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '1010010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00702: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '1010010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00703: Output = NZ  Instr=D5 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1010010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00704: Output = NZ  Instr=D6 SET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1010010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '101001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1010010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1010010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
00705: Output = Z  Instr=D7 ADD B1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '101001x000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
00706: Output = NZ  Instr=D8 SET T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '101001x000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00707: Output = NZ  Instr=D8A INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '1010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00708: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '1010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00709: Output = NZ  Instr=D5 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00710: Output = NZ  Instr=D6 SET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
00711: Output = Z  Instr=D7 ADD B1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1010011x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
00712: Output = NZ  Instr=D8 SET T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1010011x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00713: Output = NZ  Instr=D8A INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00714: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00715: Output = NZ  Instr=D5 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00716: Output = Z  Instr=D6 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '10100111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00717: Output = Z  Instr=D7 ADD B1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '10100111x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00718: Output = Z  Instr=D8 RESET T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '10100111x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00719: Output = NZ  Instr=D8A INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00720: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00721: Output = NZ  Instr=D5 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00722: Output = Z  Instr=D6 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '101001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00723: Output = Z  Instr=D7 ADD B1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '101001110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00724: Output = Z  Instr=D8 RESET T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '101001110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00725: Output = NZ  Instr=D8A INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00726: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00727: Output = NZ  Instr=D5 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00728: Output = Z  Instr=D6 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00729: Output = Z  Instr=D7 ADD B1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1010011100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00730: Output = Z  Instr=D8 RESET T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1010011100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00731: Output = NZ  Instr=D8A INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00732: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00733: Output = NZ  Instr=D5 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00734: Output = Z  Instr=D6 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '10100111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00735: Output = Z  Instr=D7 ADD B1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '10100111000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00736: Output = Z  Instr=D8 RESET T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '10100111000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00737: Output = NZ  Instr=D8A INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00738: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00739: Output = NZ  Instr=D5 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00740: Output = Z  Instr=D6 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '101001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00741: Output = Z  Instr=D7 ADD B1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '101001110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00742: Output = Z  Instr=D8 RESET T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '101001110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00743: Output = NZ  Instr=D8A INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00744: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00745: Output = NZ  Instr=D5 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00746: Output = Z  Instr=D6 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00747: Output = Z  Instr=D7 ADD B1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1010011100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00748: Output = Z  Instr=D8 RESET T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1010011100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00749: Output = NZ  Instr=D8A INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00750: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00751: Output = NZ  Instr=D5 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00752: Output = Z  Instr=D6 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '10100111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00753: Output = Z  Instr=D7 ADD B1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '10100111000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00754: Output = Z  Instr=D8 RESET T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '10100111000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00755: Output = NZ  Instr=D8A INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00756: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00757: Output = NZ  Instr=D5 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00758: Output = Z  Instr=D6 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '101001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00759: Output = Z  Instr=D7 ADD B1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '101001110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00760: Output = Z  Instr=D8 RESET T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '101001110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00761: Output = NZ  Instr=D8A INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00762: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00763: Output = NZ  Instr=D5 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00764: Output = Z  Instr=D6 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00765: Output = Z  Instr=D7 ADD B1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1010011100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00766: Output = Z  Instr=D8 RESET T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1010011100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00767: Output = NZ  Instr=D8A INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00768: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00769: Output = NZ  Instr=D5 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00770: Output = Z  Instr=D6 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '10100111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00771: Output = Z  Instr=D7 ADD B1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '10100111000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00772: Output = Z  Instr=D8 RESET T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '10100111000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00773: Output = NZ  Instr=D8A INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00774: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00775: Output = Z  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00776: Output = NZ  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00777: Output = NZ  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00778: Output = NZ  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00779: Output = NZ  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00780: Output = NZ  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00781: Output = NZ  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00782: Output = NZ  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00783: Output = NZ  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00784: Output = NZ  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00785: Output = NZ  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00786: Output = NZ  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00787: Output = NZ  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00788: Output = NZ  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00789: Output = NZ  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00790: Output = NZ  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00791: Output = NZ  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00792: Output = NZ  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00793: Output = NZ  Instr=D9 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00794: Output = Z  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00795: Output = NZ  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00796: Output = NZ  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [16, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00797: Output = NZ  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [15, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00798: Output = NZ  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [14, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00799: Output = NZ  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [13, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00800: Output = NZ  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [12, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00801: Output = NZ  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00802: Output = NZ  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [10, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00803: Output = NZ  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [9, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00804: Output = NZ  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [8, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00805: Output = NZ  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [7, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00806: Output = NZ  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [6, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00807: Output = NZ  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [5, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00808: Output = NZ  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [4, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00809: Output = NZ  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [3, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00810: Output = NZ  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [2, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00811: Output = NZ  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [1, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00812: Output = NZ  Instr=D10 DEC T4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00813: Output = Z  Instr=D1 TDEC R4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00814: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00815: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00816: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00817: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00818: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00819: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00820: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00821: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00822: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00823: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00824: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00825: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00826: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00827: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00828: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00829: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00830: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00831: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00832: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00833: Output = Z  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00834: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00835: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00836: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00837: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00838: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00839: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00840: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00841: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00842: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00843: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00844: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00845: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00846: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00847: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00848: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00849: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00850: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00851: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00852: Output = Z  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00853: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00854: Output = NZ  Instr=D6 SET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
00855: Output = NZ  Instr=D7 ADD B0; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
00856: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00857: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00858: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00859: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00860: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00861: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0x10011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00862: Output = NZ  Instr=D8 SET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0x10011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00863: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00864: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00865: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00866: Output = NZ  Instr=D6 SET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '10x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
00867: Output = NZ  Instr=D7 ADD B0; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '01x0011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
00868: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '01x0011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00869: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00870: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00871: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00872: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '101x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00873: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '010x011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00874: Output = NZ  Instr=D8 SET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '010x011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '0101011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00875: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '0101011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00876: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '0101011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00877: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0101011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00878: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0101011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0101011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00879: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0101x11100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00880: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0101x11100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0101011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00881: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '0101011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00882: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '0101011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00883: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0101011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00884: Output = NZ  Instr=D6 SET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0101011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '10100x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0101011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0101011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
00885: Output = NZ  Instr=D7 ADD B0; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '01010x1100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
00886: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '01010x1100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00887: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00888: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00889: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00890: Output = NZ  Instr=D6 SET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '101001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
00891: Output = NZ  Instr=D7 ADD B0; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '010100x100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
00892: Output = NZ  Instr=D8 SET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '010100x100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00893: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00894: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00895: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00896: Output = NZ  Instr=D6 SET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
00897: Output = NZ  Instr=D7 ADD B0; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0101001x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
00898: Output = NZ  Instr=D8 SET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0101001x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00899: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00900: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00901: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00902: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '10100111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '0101001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00903: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '01010011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
00904: Output = NZ  Instr=D8 SET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '01010011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00905: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00906: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00907: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00908: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '101001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00909: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '010100111x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00910: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '010100111x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00911: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00912: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00913: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00914: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00915: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0101001110x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00916: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0101001110x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00917: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00918: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00919: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00920: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '10100111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00921: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '01010011100x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00922: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '01010011100x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00923: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00924: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00925: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00926: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '101001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00927: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '010100111000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00928: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '010100111000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00929: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00930: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00931: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00932: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00933: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0101001110000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00934: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0101001110000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00935: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00936: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00937: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00938: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '10100111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00939: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '01010011100000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00940: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '01010011100000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00941: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00942: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00943: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00944: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '101001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00945: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '010100111000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00946: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '010100111000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00947: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00948: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00949: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00950: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00951: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0101001110000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00952: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0101001110000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00953: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00954: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00955: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00956: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '10100111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00957: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '01010011100000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00958: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '01010011100000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00959: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00960: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00961: Output = Z  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00962: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00963: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00964: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00965: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00966: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00967: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00968: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00969: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00970: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00971: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00972: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00973: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00974: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00975: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00976: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00977: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00978: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00979: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00980: Output = Z  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00981: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00982: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [16, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00983: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [15, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00984: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [14, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00985: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [13, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00986: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [12, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00987: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00988: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [10, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00989: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [9, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00990: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [8, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00991: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [7, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00992: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [6, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00993: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [5, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00994: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [4, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00995: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [3, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00996: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [2, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00997: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [1, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00998: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
00999: Output = Z  Instr=D1 TDEC R4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01000: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01001: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01002: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01003: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01004: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01005: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01006: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01007: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01008: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01009: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01010: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01011: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01012: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01013: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01014: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01015: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01016: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01017: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01018: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01019: Output = Z  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01020: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01021: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01022: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01023: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01024: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01025: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01026: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01027: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01028: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01029: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01030: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01031: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01032: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01033: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01034: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01035: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01036: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01037: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01038: Output = Z  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01039: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01040: Output = NZ  Instr=D6 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01041: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01042: Output = NZ  Instr=D8 SET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01043: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '1101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01044: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '1101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01045: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01046: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01047: Output = NZ  Instr=D7 ADD B0; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1x01001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01048: Output = NZ  Instr=D8 SET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1x01001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01049: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '1101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01050: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '1101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01051: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01052: Output = NZ  Instr=D6 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '10x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1101001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01053: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '11x1001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01054: Output = NZ  Instr=D8 SET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '11x1001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01055: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01056: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01057: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01058: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '101x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01059: Output = NZ  Instr=D7 ADD B0; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '111x001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01060: Output = NZ  Instr=D8 SET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '111x001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01061: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01062: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01063: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01064: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01065: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1111x01110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01066: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1111x01110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01067: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01068: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01069: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01070: Output = NZ  Instr=D6 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '10100x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1111001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01071: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '11110x1110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01072: Output = NZ  Instr=D8 SET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '11110x1110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1111011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01073: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '1111011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01074: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '1111011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01075: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1111011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01076: Output = NZ  Instr=D6 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1111011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '101001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1111011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1111011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01077: Output = NZ  Instr=D7 ADD B0; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '111101x110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01078: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '111101x110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1111010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01079: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '1111010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01080: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '1111010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01081: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1111010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01082: Output = NZ  Instr=D6 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1111010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1111010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1111010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01083: Output = NZ  Instr=D7 ADD B0; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1111010x10000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01084: Output = NZ  Instr=D8 SET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1111010x10000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1111010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01085: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '1111010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01086: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '1111010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01087: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1111010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01088: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1111010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '10100111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1111010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01089: Output = NZ  Instr=D7 ADD B0; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '11110101x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01090: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '11110101x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1111010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01091: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '1111010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01092: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '1111010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01093: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1111010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01094: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1111010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '101001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1111010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01095: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '111101010x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01096: Output = NZ  Instr=D8 SET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '111101010x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01097: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01098: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01099: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01100: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01101: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1111010101x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01102: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1111010101x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01103: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01104: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01105: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01106: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '10100111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01107: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '11110101010x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01108: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '11110101010x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01109: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01110: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01111: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01112: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '101001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01113: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '111101010100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01114: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '111101010100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01115: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01116: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01117: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01118: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01119: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1111010101000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01120: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1111010101000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01121: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01122: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01123: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01124: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '10100111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01125: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '11110101010000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01126: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '11110101010000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01127: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01128: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01129: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01130: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '101001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01131: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '111101010100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01132: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '111101010100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01133: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01134: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01135: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01136: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01137: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1111010101000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01138: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1111010101000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01139: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01140: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01141: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01142: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '10100111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01143: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '11110101010000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01144: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '11110101010000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01145: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01146: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01147: Output = Z  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01148: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01149: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01150: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01151: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01152: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01153: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01154: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01155: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01156: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01157: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01158: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01159: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01160: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01161: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01162: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01163: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01164: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01165: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01166: Output = Z  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01167: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01168: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [16, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01169: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [15, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01170: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [14, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01171: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [13, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01172: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [12, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01173: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01174: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [10, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01175: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [9, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01176: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [8, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01177: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [7, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01178: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [6, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01179: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [5, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01180: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [4, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01181: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [3, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01182: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [2, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01183: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [1, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01184: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01185: Output = Z  Instr=D1 TDEC R4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01186: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01187: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01188: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01189: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01190: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01191: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01192: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01193: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01194: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01195: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01196: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01197: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01198: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01199: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01200: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01201: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01202: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01203: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01204: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01205: Output = Z  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01206: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01207: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01208: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01209: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01210: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01211: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01212: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01213: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01214: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01215: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01216: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01217: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01218: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01219: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01220: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01221: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01222: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01223: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01224: Output = Z  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01225: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01226: Output = NZ  Instr=D6 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01227: Output = NZ  Instr=D7 ADD B0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01228: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01229: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '0111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01230: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '0111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01231: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01232: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0111010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01233: Output = NZ  Instr=D7 ADD B0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0x11010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01234: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0x11010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01235: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01236: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01237: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01238: Output = NZ  Instr=D6 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '10x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01239: Output = NZ  Instr=D7 ADD B0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '00x1010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01240: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '00x1010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01241: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01242: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01243: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01244: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '101x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01245: Output = NZ  Instr=D7 ADD B0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '001x010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01246: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '001x010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01247: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01248: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01249: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01250: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01251: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0010x10101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01252: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0010x10101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0010110101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01253: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '0010110101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01254: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '0010110101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01255: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0010110101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01256: Output = NZ  Instr=D6 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0010110101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '10100x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0010110101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0010110101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01257: Output = NZ  Instr=D7 ADD B0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '00101x0101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01258: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '00101x0101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01259: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01260: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01261: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01262: Output = NZ  Instr=D6 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '101001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01263: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '001010x101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01264: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '001010x101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01265: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01266: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01267: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01268: Output = NZ  Instr=D6 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01269: Output = NZ  Instr=D7 ADD B0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0010100x01000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01270: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0010100x01000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01271: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01272: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01273: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01274: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '10100111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '0010100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01275: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '00101001x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01276: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '00101001x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01277: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01278: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01279: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01280: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '101001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01281: Output = NZ  Instr=D7 ADD B0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '001010011x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01282: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '001010011x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01283: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01284: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01285: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01286: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01287: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0010100111x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01288: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0010100111x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01289: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01290: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01291: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01292: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '10100111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01293: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '00101001110x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01294: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '00101001110x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01295: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01296: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01297: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01298: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '101001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01299: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '001010011100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01300: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '001010011100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01301: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01302: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01303: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01304: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01305: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0010100111000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01306: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0010100111000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01307: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01308: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01309: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01310: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '10100111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01311: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '00101001110000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01312: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '00101001110000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01313: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01314: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01315: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01316: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '101001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01317: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '001010011100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01318: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '001010011100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01319: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01320: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01321: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01322: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01323: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0010100111000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01324: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0010100111000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01325: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01326: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01327: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01328: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '10100111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01329: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '00101001110000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01330: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '00101001110000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01331: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01332: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01333: Output = Z  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01334: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01335: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01336: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01337: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01338: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01339: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01340: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01341: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01342: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01343: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01344: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01345: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01346: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01347: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01348: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01349: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01350: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01351: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01352: Output = Z  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01353: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01354: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [16, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01355: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [15, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01356: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [14, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01357: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [13, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01358: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [12, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01359: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01360: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [10, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01361: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [9, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01362: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [8, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01363: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [7, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01364: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [6, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01365: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [5, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01366: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [4, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01367: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [3, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01368: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [2, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01369: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [1, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01370: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01371: Output = Z  Instr=D1 TDEC R4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01372: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01373: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01374: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01375: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01376: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01377: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01378: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01379: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01380: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01381: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01382: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01383: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01384: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01385: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01386: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01387: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01388: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01389: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01390: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01391: Output = Z  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01392: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01393: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01394: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01395: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01396: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01397: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01398: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01399: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01400: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01401: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01402: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01403: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01404: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01405: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01406: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01407: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01408: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01409: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01410: Output = Z  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01411: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01412: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01413: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01414: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01415: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '1010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01416: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '1010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01417: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01418: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01419: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1x10100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01420: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1x10100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01421: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '1010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01422: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '1010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01423: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01424: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '10x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01425: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '10x0100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01426: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '10x0100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01427: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '1000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01428: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '1000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01429: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01430: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '101x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01431: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '100x100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01432: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '100x100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1001100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01433: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '1001100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01434: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '1001100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01435: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1001100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01436: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1001100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1001100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01437: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1001x00111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01438: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1001x00111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1001100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01439: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '1001100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01440: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '1001100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01441: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1001100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01442: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1001100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '10100x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1001100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1001100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01443: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '10011x0111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01444: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '10011x0111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1001110111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01445: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '1001110111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01446: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '1001110111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01447: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1001110111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01448: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1001110111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '101001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1001110111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1001110111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01449: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '100111x111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01450: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '100111x111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1001111111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01451: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '1001111111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01452: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '1001111111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01453: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1001111111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01454: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1001111111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1001111111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1001111111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01455: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1001111x11000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01456: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1001111x11000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1001111011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01457: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '1001111011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01458: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '1001111011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01459: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1001111011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01460: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1001111011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '10100111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1001111011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01461: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '10011110x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01462: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '10011110x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1001111001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01463: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '1001111001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01464: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '1001111001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01465: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1001111001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01466: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1001111001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '101001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1001111001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01467: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '100111100x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01468: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '100111100x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1001111000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01469: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '1001111000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01470: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '1001111000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01471: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1001111000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01472: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1001111000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1001111000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01473: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1001111000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01474: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1001111000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01475: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01476: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01477: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01478: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '10100111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01479: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '10011110001x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01480: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '10011110001x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01481: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01482: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01483: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01484: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '101001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01485: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '100111100010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01486: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '100111100010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01487: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01488: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01489: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01490: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01491: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1001111000100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01492: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1001111000100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01493: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01494: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01495: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01496: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '10100111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01497: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '10011110001000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01498: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '10011110001000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01499: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01500: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01501: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01502: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '101001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01503: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '100111100010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01504: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '100111100010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01505: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01506: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01507: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01508: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01509: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1001111000100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01510: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1001111000100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01511: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01512: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01513: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01514: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '10100111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01515: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '10011110001000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01516: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '10011110001000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01517: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01518: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01519: Output = Z  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01520: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01521: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01522: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01523: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01524: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01525: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01526: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01527: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01528: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01529: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01530: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01531: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01532: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01533: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01534: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01535: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01536: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01537: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01538: Output = Z  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01539: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01540: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [16, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01541: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [15, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01542: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [14, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01543: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [13, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01544: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [12, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01545: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01546: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [10, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01547: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [9, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01548: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [8, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01549: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [7, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01550: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [6, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01551: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [5, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01552: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [4, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01553: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [3, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01554: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [2, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01555: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [1, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01556: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01557: Output = Z  Instr=D1 TDEC R4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01558: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01559: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01560: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01561: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01562: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01563: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01564: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01565: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01566: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01567: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01568: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01569: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01570: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01571: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01572: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01573: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01574: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01575: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01576: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01577: Output = Z  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01578: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01579: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01580: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01581: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01582: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01583: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01584: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01585: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01586: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01587: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01588: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01589: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01590: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01591: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01592: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01593: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01594: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01595: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01596: Output = Z  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01597: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01598: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01599: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01600: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01601: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01602: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01603: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01604: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01605: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0x01111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01606: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0x01111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0101111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01607: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '0101111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01608: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '0101111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01609: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0101111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01610: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0101111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '10x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0101111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0101111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01611: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '01x1111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01612: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '01x1111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01613: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01614: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01615: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01616: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '101x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01617: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '011x111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01618: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '011x111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01619: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01620: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01621: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01622: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01623: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0111x11000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01624: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0111x11000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01625: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01626: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01627: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01628: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '10100x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0111111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01629: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '01111x1000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01630: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '01111x1000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01631: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01632: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01633: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01634: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '101001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01635: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '011110x000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01636: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '011110x000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01637: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01638: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01639: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01640: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01641: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0111101x00100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01642: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0111101x00100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01643: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01644: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01645: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01646: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '10100111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '0111101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01647: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '01111010x0100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01648: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '01111010x0100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01649: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01650: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01651: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01652: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '101001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01653: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '011110101x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01654: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '011110101x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01655: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01656: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01657: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01658: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01659: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0111101010x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01660: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0111101010x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01661: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01662: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01663: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01664: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '10100111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01665: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '01111010101x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01666: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '01111010101x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01667: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01668: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01669: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01670: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '101001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01671: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '011110101010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01672: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '011110101010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01673: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01674: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01675: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01676: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01677: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0111101010100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01678: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0111101010100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01679: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01680: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01681: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01682: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '10100111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01683: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '01111010101000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01684: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '01111010101000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01685: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01686: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01687: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01688: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '101001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01689: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '011110101010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01690: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '011110101010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01691: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01692: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01693: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01694: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01695: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0111101010100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01696: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0111101010100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01697: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01698: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01699: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01700: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '10100111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01701: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '01111010101000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01702: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '01111010101000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01703: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01704: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01705: Output = Z  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01706: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01707: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01708: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01709: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01710: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01711: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01712: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01713: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01714: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01715: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01716: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01717: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01718: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01719: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01720: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01721: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01722: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01723: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01724: Output = Z  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01725: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01726: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [16, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01727: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [15, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01728: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [14, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01729: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [13, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01730: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [12, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01731: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01732: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [10, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01733: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [9, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01734: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [8, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01735: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [7, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01736: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [6, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01737: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [5, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01738: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [4, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01739: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [3, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01740: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [2, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01741: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [1, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01742: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01743: Output = Z  Instr=D1 TDEC R4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01744: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01745: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01746: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01747: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01748: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01749: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01750: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01751: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01752: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01753: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01754: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01755: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01756: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01757: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01758: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01759: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01760: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01761: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01762: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01763: Output = Z  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01764: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01765: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01766: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01767: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01768: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01769: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01770: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01771: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01772: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01773: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01774: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01775: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01776: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01777: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01778: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01779: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01780: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01781: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01782: Output = Z  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01783: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01784: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01785: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01786: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01787: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '1111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01788: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '1111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01789: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01790: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01791: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1x11101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01792: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1x11101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01793: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '1111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01794: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '1111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01795: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01796: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '10x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1111101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01797: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '11x1101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01798: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '11x1101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1101101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01799: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '1101101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01800: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '1101101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01801: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1101101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01802: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1101101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '101x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1101101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01803: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '110x101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01804: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '110x101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01805: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '1100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01806: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '1100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01807: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01808: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01809: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1100x01010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01810: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1100x01010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01811: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01812: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01813: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01814: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '10100x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01815: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '11000x1010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01816: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '11000x1010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01817: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01818: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01819: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01820: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '101001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01821: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '110000x010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01822: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '110000x010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01823: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01824: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01825: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01826: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01827: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1100001x10100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01828: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1100001x10100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01829: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01830: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01831: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01832: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '10100111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1100001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01833: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '11000010x0100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01834: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '11000010x0100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1100001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01835: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '1100001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01836: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '1100001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01837: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1100001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01838: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1100001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '101001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1100001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01839: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '110000100x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01840: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '110000100x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01841: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01842: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01843: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01844: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01845: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1100001001x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01846: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1100001001x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01847: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01848: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01849: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01850: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '10100111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01851: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '11000010011x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01852: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '11000010011x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01853: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01854: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01855: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01856: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '101001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01857: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '110000100110x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01858: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '110000100110x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01859: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01860: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01861: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01862: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01863: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1100001001100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01864: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1100001001100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01865: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01866: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01867: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01868: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '10100111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01869: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '11000010011000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01870: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '11000010011000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01871: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01872: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01873: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01874: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '101001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01875: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '110000100110000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01876: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '110000100110000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01877: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01878: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01879: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01880: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01881: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1100001001100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01882: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1100001001100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01883: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01884: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01885: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01886: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '10100111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01887: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '11000010011000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01888: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '11000010011000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01889: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01890: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01891: Output = Z  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01892: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01893: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01894: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01895: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01896: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01897: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01898: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01899: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01900: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01901: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01902: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01903: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01904: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01905: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01906: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01907: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01908: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01909: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01910: Output = Z  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01911: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01912: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [16, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01913: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [15, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01914: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [14, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01915: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [13, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01916: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [12, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01917: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01918: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [10, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01919: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [9, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01920: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [8, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01921: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [7, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01922: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [6, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01923: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [5, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01924: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [4, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01925: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [3, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01926: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [2, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01927: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [1, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01928: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01929: Output = Z  Instr=D1 TDEC R4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01930: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01931: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01932: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01933: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01934: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01935: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01936: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01937: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01938: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01939: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01940: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01941: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01942: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01943: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01944: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01945: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01946: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01947: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01948: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01949: Output = Z  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01950: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01951: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01952: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01953: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01954: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01955: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01956: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01957: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01958: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01959: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01960: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01961: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01962: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01963: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01964: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01965: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01966: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01967: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01968: Output = Z  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01969: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01970: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01971: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
01972: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01973: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '0100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01974: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '0100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01975: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01976: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0100001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01977: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0x00001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01978: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0x00001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '0000001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01979: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '0000001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01980: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '0000001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01981: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0000001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01982: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0000001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '10x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0000001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0000001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01983: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '00x0001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
01984: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '00x0001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '0000001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01985: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '0000001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01986: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '0000001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01987: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '0000001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01988: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '0000001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '101x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '0000001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01989: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '000x001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
01990: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '000x001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '0001001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01991: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '0001001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01992: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '0001001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01993: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0001001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01994: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0001001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0001001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01995: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0001x01001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01996: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0001x01001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '0001001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01997: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '0001001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01998: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '0001001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
01999: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0001001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02000: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0001001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '10100x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0001001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0001001001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
02001: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '00010x1001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
02002: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '00010x1001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '0001011001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02003: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '0001011001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02004: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '0001011001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02005: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0001011001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02006: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0001011001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '101001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0001011001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0001011001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
02007: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '000101x001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
02008: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '000101x001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '0001010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02009: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '0001010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02010: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '0001010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02011: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0001010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02012: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0001010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0001010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0001010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
02013: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0001010x01100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
02014: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0001010x01100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '0001010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02015: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '0001010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02016: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '0001010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02017: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '0001010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02018: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '0001010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '10100111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '0001010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02019: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '00010100x1100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02020: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '00010100x1100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02021: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02022: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02023: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02024: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '101001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02025: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '000101001x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02026: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '000101001x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02027: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02028: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02029: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02030: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02031: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0001010011x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02032: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0001010011x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02033: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02034: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02035: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02036: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '10100111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02037: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '00010100111x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02038: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '00010100111x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02039: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02040: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02041: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02042: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '101001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02043: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '000101001110x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02044: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '000101001110x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02045: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02046: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02047: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02048: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02049: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0001010011100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02050: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0001010011100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02051: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02052: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02053: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02054: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '10100111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02055: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '00010100111000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02056: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '00010100111000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02057: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02058: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02059: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02060: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '101001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02061: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '000101001110000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02062: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '000101001110000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02063: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02064: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02065: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02066: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02067: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0001010011100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02068: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0001010011100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02069: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02070: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02071: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02072: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '10100111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02073: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '00010100111000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02074: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '00010100111000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02075: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02076: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02077: Output = Z  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02078: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02079: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02080: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02081: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02082: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02083: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02084: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02085: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02086: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02087: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02088: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02089: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02090: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02091: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02092: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02093: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02094: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02095: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02096: Output = Z  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02097: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02098: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [16, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02099: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [15, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02100: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [14, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02101: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [13, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02102: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [12, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02103: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02104: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [10, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02105: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [9, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02106: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [8, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02107: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [7, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02108: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [6, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02109: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [5, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02110: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [4, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02111: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [3, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02112: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [2, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02113: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [1, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02114: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02115: Output = Z  Instr=D1 TDEC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02116: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02117: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02118: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02119: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02120: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02121: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02122: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02123: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02124: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02125: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02126: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02127: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02128: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02129: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02130: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02131: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02132: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02133: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02134: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02135: Output = Z  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02136: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02137: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02138: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02139: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02140: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02141: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02142: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02143: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02144: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02145: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02146: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02147: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02148: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02149: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02150: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02151: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02152: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02153: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02154: Output = Z  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02155: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02156: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '0001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
02157: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
02158: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, 'x001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02159: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '1001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02160: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '1001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02161: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02162: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02163: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1x01010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02164: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1x01010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02165: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '1001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02166: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '1001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02167: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02168: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '10x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1001010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
02169: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '10x1010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
02170: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '10x1010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02171: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02172: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02173: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02174: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '101x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02175: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '101x010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02176: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '101x010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02177: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02178: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02179: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02180: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02181: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1011x10011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02182: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1011x10011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02183: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02184: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02185: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02186: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '10100x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1011010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
02187: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '10110x0011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
02188: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '10110x0011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02189: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02190: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02191: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02192: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '101001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
02193: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '101100x011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
02194: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '101100x011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02195: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02196: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02197: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02198: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
02199: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1011000x11100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
02200: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1011000x11100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02201: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02202: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02203: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02204: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '10100111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1011000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02205: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '10110000x1100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02206: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '10110000x1100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1011000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02207: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '1011000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02208: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '1011000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02209: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1011000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02210: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1011000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '101001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1011000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02211: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '101100000x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02212: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '101100000x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1011000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02213: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '1011000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02214: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '1011000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02215: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1011000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02216: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1011000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1011000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02217: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1011000000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02218: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1011000000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1011000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02219: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '1011000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02220: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '1011000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02221: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1011000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02222: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1011000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '10100111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1011000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02223: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '10110000000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
02224: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '10110000000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02225: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02226: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02227: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02228: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '101001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02229: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '101100000001x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02230: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '101100000001x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02231: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02232: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02233: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02234: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02235: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1011000000010x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02236: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1011000000010x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02237: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02238: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02239: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02240: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '10100111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02241: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '10110000000100x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02242: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '10110000000100x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02243: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02244: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02245: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02246: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '101001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02247: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '101100000001000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02248: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '101100000001000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02249: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02250: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02251: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02252: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02253: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1011000000010000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02254: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1011000000010000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02255: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02256: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02257: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02258: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '10100111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02259: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '10110000000100000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02260: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '10110000000100000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02261: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02262: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02263: Output = Z  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02264: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02265: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02266: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02267: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02268: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02269: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02270: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02271: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02272: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02273: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02274: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02275: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02276: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02277: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02278: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02279: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02280: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02281: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02282: Output = Z  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02283: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02284: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [16, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02285: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [15, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02286: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [14, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02287: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [13, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02288: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [12, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02289: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02290: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [10, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02291: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [9, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02292: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [8, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02293: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [7, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02294: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [6, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02295: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [5, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02296: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [4, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02297: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [3, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02298: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [2, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02299: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [1, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02300: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02301: Output = Z  Instr=D1 TDEC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02302: Output = Z  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02303: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02304: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02305: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02306: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02307: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02308: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02309: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02310: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02311: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02312: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02313: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02314: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02315: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02316: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02317: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02318: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02319: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02320: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02321: Output = Z  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02322: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02323: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02324: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02325: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02326: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02327: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02328: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02329: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02330: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02331: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02332: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02333: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02334: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02335: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02336: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02337: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02338: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02339: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02340: Output = Z  Instr=COMP NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02341: Output = Z  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02342: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02343: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02344: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 9, 'T4': [1, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02345: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02346: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [1, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02347: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 9, 'T4': [2, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02348: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02349: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [2, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02350: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 9, 'T4': [3, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02351: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02352: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [3, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02353: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 9, 'T4': [4, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02354: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02355: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [4, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02356: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 9, 'T4': [5, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02357: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02358: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [5, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02359: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 9, 'T4': [6, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02360: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02361: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [6, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02362: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 9, 'T4': [7, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02363: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02364: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [7, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02365: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 9, 'T4': [8, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02366: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '000010011'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02367: Output = Z  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [8, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02368: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 9, 'T4': [9, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02369: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02370: Output = Z  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [9, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '00001001100'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02371: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 9, 'T4': [10, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '00001001100'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02372: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '00001001100'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02373: Output = Z  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [10, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '000010011000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02374: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '000010011000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02375: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '000010011000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02376: Output = Z  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02377: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 9, 'T4': [12, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02378: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02379: Output = Z  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [12, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '00001001100000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02380: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 9, 'T4': [13, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '00001001100000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02381: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '00001001100000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02382: Output = Z  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [13, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '000010011000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02383: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 9, 'T4': [14, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '000010011000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02384: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '000010011000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02385: Output = Z  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [14, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02386: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 9, 'T4': [15, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02387: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02388: Output = Z  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [15, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '00001001100000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02389: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 9, 'T4': [16, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '00001001100000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02390: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '00001001100000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02391: Output = Z  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [16, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '000010011000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02392: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 9, 'T4': [17, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '000010011000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02393: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '000010011000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02394: Output = Z  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02395: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02396: Output = Z  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02397: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '000010011000000000x'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02398: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '101100000001000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [18, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02399: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02400: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02401: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '00001001100000000x0'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02402: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '10110000000100000x0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [17, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02403: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [16, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02404: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [16, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02405: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [16, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000x00'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [16, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02406: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [16, '1011000000010000x00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [16, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02407: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [15, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02408: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [15, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02409: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [15, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '000010011000000x000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [15, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02410: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [15, '101100000001000x000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [15, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02411: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [14, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02412: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [14, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02413: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [14, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '00001001100000x0000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [14, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02414: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [14, '10110000000100x0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [14, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02415: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [13, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02416: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [13, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02417: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [13, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000x00000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [13, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02418: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [13, '1011000000010x00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [13, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02419: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [12, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02420: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [12, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02421: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [12, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '000010011000x000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [12, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02422: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [12, '101100000001x000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [12, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02423: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02424: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02425: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '00001001100x0000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02426: Output = NZ  Instr=E9 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '10110000000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02427: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02428: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02429: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02430: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02431: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02432: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02433: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02434: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02435: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02436: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02437: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02438: Output = Z  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [11, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02439: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [10, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02440: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [9, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02441: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [8, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02442: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [7, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02443: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [6, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02444: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [5, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02445: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [4, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02446: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [3, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02447: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [2, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02448: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [1, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02449: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02450: Output = Z  Instr=E11 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 9, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02451: Output = NZ  Instr=EVL NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02452: Output = Z  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02453: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02454: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02455: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02456: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02457: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02458: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02459: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02460: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02461: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02462: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02463: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02464: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02465: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02466: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02467: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02468: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02469: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02470: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02471: Output = Z  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02472: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02473: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02474: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02475: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02476: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02477: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02478: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02479: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02480: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02481: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02482: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02483: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02484: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02485: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02486: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02487: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02488: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02489: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02490: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02491: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '1011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02492: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, 'x011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02493: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [1, '0011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02494: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02495: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0x11000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02496: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [2, '0011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02497: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0011000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02498: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '00x1000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0001000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02499: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [3, '0001000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02500: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0001000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02501: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '000x000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02502: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [4, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02503: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02504: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0000x00000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02505: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [5, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02506: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02507: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '00000x0000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02508: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [6, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02509: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02510: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '000000x000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02511: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [7, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02512: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02513: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000000x00010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02514: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [8, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02515: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02516: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '00000000x0010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02517: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [9, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02518: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02519: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '000000000x010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02520: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [10, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02521: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02522: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0000000000x10000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02523: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [11, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02524: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0000000000010000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02525: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '00000000000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02526: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02527: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02528: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '000000000000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02529: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02530: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02531: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0000000000000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02532: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02533: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02534: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '00000000000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02535: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02536: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02537: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '000000000000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02538: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02539: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02540: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0000000000000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02541: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02542: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02543: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '00000000000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02544: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02545: Output = Z  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02546: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02547: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02548: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02549: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02550: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02551: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02552: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02553: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02554: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [9, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02555: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [8, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02556: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [7, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02557: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [6, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02558: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [5, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02559: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [4, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02560: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [3, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02561: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02562: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02563: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02564: Output = Z  Instr=B5 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02565: Output = Z  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02566: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02567: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02568: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02569: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02570: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02571: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02572: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02573: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 8, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02574: Output = Z  Instr=B7 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 8, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02575: Output = NZ  Instr=B7 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 0, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02576: Output = NZ  Instr=B7 INC R3; regs={'R4': 1, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 1, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02577: Output = NZ  Instr=B7 INC R3; regs={'R4': 2, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 2, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02578: Output = NZ  Instr=B7 INC R3; regs={'R4': 3, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 3, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 4, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02579: Output = NZ  Instr=B7 INC R3; regs={'R4': 4, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 4, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 5, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02580: Output = NZ  Instr=B7 INC R3; regs={'R4': 5, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 5, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 6, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02581: Output = NZ  Instr=B7 INC R3; regs={'R4': 6, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 6, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 7, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02582: Output = NZ  Instr=B7 INC R3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02583: Output = Z  Instr=B8 NOP; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02584: Output = Z  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02585: Output = NZ  Instr=B9 INC R1; regs={'R4': 8, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02586: Output = NZ  Instr=B9 INC R1; regs={'R4': 8, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02587: Output = NZ  Instr=B9 INC R1; regs={'R4': 8, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02588: Output = NZ  Instr=B9 INC R1; regs={'R4': 8, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02589: Output = NZ  Instr=B9 INC R1; regs={'R4': 8, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02590: Output = NZ  Instr=B9 INC R1; regs={'R4': 8, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02591: Output = NZ  Instr=B9 INC R1; regs={'R4': 8, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02592: Output = NZ  Instr=B9 INC R1; regs={'R4': 8, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02593: Output = NZ  Instr=B9 INC R1; regs={'R4': 8, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02594: Output = NZ  Instr=B9 INC R1; regs={'R4': 8, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02595: Output = NZ  Instr=B9 INC R1; regs={'R4': 8, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02596: Output = NZ  Instr=B9 INC R1; regs={'R4': 8, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02597: Output = NZ  Instr=B9 INC R1; regs={'R4': 8, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02598: Output = NZ  Instr=B9 INC R1; regs={'R4': 8, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02599: Output = NZ  Instr=B9 INC R1; regs={'R4': 8, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02600: Output = NZ  Instr=B9 INC R1; regs={'R4': 8, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02601: Output = NZ  Instr=B9 INC R1; regs={'R4': 8, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02602: Output = NZ  Instr=B9 INC R1; regs={'R4': 8, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 8, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02603: Output = Z  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02604: Output = NZ  Instr=B10 INC R0; regs={'R4': 8, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 8, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02605: Output = NZ  Instr=B10 INC R0; regs={'R4': 8, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 8, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02606: Output = NZ  Instr=B10 INC R0; regs={'R4': 8, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 8, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02607: Output = NZ  Instr=B10 INC R0; regs={'R4': 8, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 8, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02608: Output = NZ  Instr=B10 INC R0; regs={'R4': 8, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 8, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02609: Output = NZ  Instr=B10 INC R0; regs={'R4': 8, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 8, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02610: Output = NZ  Instr=B10 INC R0; regs={'R4': 8, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 8, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02611: Output = NZ  Instr=B10 INC R0; regs={'R4': 8, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 8, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02612: Output = NZ  Instr=B10 INC R0; regs={'R4': 8, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 8, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02613: Output = NZ  Instr=B10 INC R0; regs={'R4': 8, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 8, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02614: Output = NZ  Instr=B10 INC R0; regs={'R4': 8, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 8, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02615: Output = NZ  Instr=B10 INC R0; regs={'R4': 8, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 8, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02616: Output = NZ  Instr=B10 INC R0; regs={'R4': 8, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 8, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02617: Output = NZ  Instr=B10 INC R0; regs={'R4': 8, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 8, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02618: Output = NZ  Instr=B10 INC R0; regs={'R4': 8, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 8, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02619: Output = NZ  Instr=B10 INC R0; regs={'R4': 8, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 8, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02620: Output = NZ  Instr=B10 INC R0; regs={'R4': 8, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 8, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02621: Output = NZ  Instr=B10 INC R0; regs={'R4': 8, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02622: Output = Z  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02623: Output = NZ  Instr=B12 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02624: Output = NZ  Instr=B13 READ T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02625: Output = Z  Instr=B14 RESET T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, 'x011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02626: Output = NZ  Instr=B15 INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02627: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02628: Output = NZ  Instr=B12 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02629: Output = Z  Instr=B13 READ T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02630: Output = Z  Instr=B14 RESET T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [1, '0x11101100000000000'], 'T3': [1, '0x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02631: Output = NZ  Instr=B15 INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02632: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02633: Output = NZ  Instr=B12 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02634: Output = NZ  Instr=B13 READ T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02635: Output = NZ  Instr=B14 SET T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [2, '00x1101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02636: Output = NZ  Instr=B15 INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02637: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02638: Output = NZ  Instr=B12 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02639: Output = Z  Instr=B13 READ T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02640: Output = NZ  Instr=B14 SET T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [3, '001x101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02641: Output = NZ  Instr=B15 INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [3, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02642: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02643: Output = NZ  Instr=B12 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02644: Output = Z  Instr=B13 READ T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02645: Output = NZ  Instr=B14 SET T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011x01100000000000'], 'T3': [4, '0011x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02646: Output = NZ  Instr=B15 INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [4, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02647: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02648: Output = NZ  Instr=B12 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02649: Output = NZ  Instr=B13 READ T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02650: Output = Z  Instr=B14 RESET T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [5, '00111x1100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02651: Output = NZ  Instr=B15 INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02652: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02653: Output = NZ  Instr=B12 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02654: Output = NZ  Instr=B13 READ T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02655: Output = NZ  Instr=B14 SET T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [6, '001110x100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02656: Output = NZ  Instr=B15 INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02657: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02658: Output = NZ  Instr=B12 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02659: Output = NZ  Instr=B13 READ T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02660: Output = NZ  Instr=B14 SET T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101x00000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02661: Output = NZ  Instr=B15 INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02662: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02663: Output = NZ  Instr=B12 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02664: Output = Z  Instr=B13 READ T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02665: Output = Z  Instr=B14 RESET T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [8, '00111011x0000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02666: Output = NZ  Instr=B15 INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02667: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02668: Output = NZ  Instr=B12 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02669: Output = Z  Instr=B13 READ T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02670: Output = Z  Instr=B14 RESET T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [9, '001110110x000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02671: Output = NZ  Instr=B15 INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02672: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02673: Output = NZ  Instr=B12 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02674: Output = Z  Instr=B13 READ T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02675: Output = Z  Instr=B14 RESET T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100x00000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02676: Output = NZ  Instr=B15 INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02677: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02678: Output = NZ  Instr=B12 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02679: Output = Z  Instr=B13 READ T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02680: Output = Z  Instr=B14 RESET T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [11, '00111011000x0000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02681: Output = NZ  Instr=B15 INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02682: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02683: Output = NZ  Instr=B12 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02684: Output = Z  Instr=B13 READ T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02685: Output = Z  Instr=B14 RESET T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [12, '001110110000x000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02686: Output = NZ  Instr=B15 INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02687: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02688: Output = NZ  Instr=B12 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02689: Output = Z  Instr=B13 READ T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02690: Output = Z  Instr=B14 RESET T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000x00000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02691: Output = NZ  Instr=B15 INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02692: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02693: Output = NZ  Instr=B12 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02694: Output = Z  Instr=B13 READ T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02695: Output = Z  Instr=B14 RESET T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [14, '00111011000000x0000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02696: Output = NZ  Instr=B15 INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02697: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02698: Output = NZ  Instr=B12 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02699: Output = Z  Instr=B13 READ T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02700: Output = Z  Instr=B14 RESET T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [15, '001110110000000x000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02701: Output = NZ  Instr=B15 INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02702: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02703: Output = NZ  Instr=B12 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02704: Output = Z  Instr=B13 READ T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02705: Output = Z  Instr=B14 RESET T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000x00'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02706: Output = NZ  Instr=B15 INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02707: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02708: Output = NZ  Instr=B12 READ T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02709: Output = Z  Instr=B13 READ T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02710: Output = Z  Instr=B14 RESET T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [17, '00111011000000000x0'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02711: Output = NZ  Instr=B15 INC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02712: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02713: Output = Z  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02714: Output = NZ  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02715: Output = NZ  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02716: Output = NZ  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02717: Output = NZ  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02718: Output = NZ  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02719: Output = NZ  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02720: Output = NZ  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02721: Output = NZ  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02722: Output = NZ  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02723: Output = NZ  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02724: Output = NZ  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02725: Output = NZ  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02726: Output = NZ  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02727: Output = NZ  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02728: Output = NZ  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02729: Output = NZ  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02730: Output = NZ  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02731: Output = NZ  Instr=B16 DEC T2; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02732: Output = Z  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02733: Output = NZ  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02734: Output = NZ  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02735: Output = NZ  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02736: Output = NZ  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02737: Output = NZ  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02738: Output = NZ  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02739: Output = NZ  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02740: Output = NZ  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02741: Output = NZ  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02742: Output = NZ  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02743: Output = NZ  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02744: Output = NZ  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02745: Output = NZ  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02746: Output = NZ  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02747: Output = NZ  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02748: Output = NZ  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02749: Output = NZ  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02750: Output = NZ  Instr=B17 DEC T3; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02751: Output = Z  Instr=ADD NOP; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02752: Output = Z  Instr=C1 TDEC R4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02753: Output = NZ  Instr=C2 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02754: Output = Z  Instr=C4 SET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02755: Output = Z  Instr=C1 TDEC R4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02756: Output = NZ  Instr=C2 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02757: Output = NZ  Instr=C3 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02758: Output = NZ  Instr=C2 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02759: Output = Z  Instr=C4 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02760: Output = NZ  Instr=C4 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02761: Output = Z  Instr=C1 TDEC R4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02762: Output = NZ  Instr=C2 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02763: Output = Z  Instr=C4 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02764: Output = Z  Instr=C1 TDEC R4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02765: Output = NZ  Instr=C2 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02766: Output = NZ  Instr=C3 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02767: Output = NZ  Instr=C2 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02768: Output = NZ  Instr=C3 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02769: Output = NZ  Instr=C2 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02770: Output = NZ  Instr=C3 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x1101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0001101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02771: Output = NZ  Instr=C2 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0001101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02772: Output = NZ  Instr=C3 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '000x101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02773: Output = NZ  Instr=C2 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02774: Output = NZ  Instr=C3 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000x01100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000001100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02775: Output = NZ  Instr=C2 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000001100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02776: Output = Z  Instr=C4 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '00000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02777: Output = NZ  Instr=C4 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02778: Output = NZ  Instr=C4 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02779: Output = NZ  Instr=C4 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02780: Output = NZ  Instr=C4 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02781: Output = NZ  Instr=C4 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02782: Output = Z  Instr=C1 TDEC R4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02783: Output = NZ  Instr=C2 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02784: Output = Z  Instr=C4 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02785: Output = Z  Instr=C1 TDEC R4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02786: Output = NZ  Instr=C2 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02787: Output = NZ  Instr=C3 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02788: Output = NZ  Instr=C2 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02789: Output = Z  Instr=C4 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02790: Output = NZ  Instr=C4 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02791: Output = Z  Instr=C1 TDEC R4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02792: Output = NZ  Instr=C2 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02793: Output = Z  Instr=C4 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02794: Output = Z  Instr=C1 TDEC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02795: Output = NZ  Instr=C2 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02796: Output = NZ  Instr=C3 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02797: Output = NZ  Instr=C2 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02798: Output = NZ  Instr=C3 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02799: Output = NZ  Instr=C2 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02800: Output = Z  Instr=C4 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02801: Output = NZ  Instr=C4 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02802: Output = NZ  Instr=C4 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02803: Output = Z  Instr=C1 TDEC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02804: Output = Z  Instr=C5 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02805: Output = Z  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02806: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02807: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02808: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02809: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02810: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02811: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02812: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02813: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 8, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02814: Output = Z  Instr=C7 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 8, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02815: Output = NZ  Instr=C7 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 0, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02816: Output = NZ  Instr=C7 INC R3; regs={'R4': 1, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 1, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02817: Output = NZ  Instr=C7 INC R3; regs={'R4': 2, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 2, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02818: Output = NZ  Instr=C7 INC R3; regs={'R4': 3, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 3, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 4, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02819: Output = NZ  Instr=C7 INC R3; regs={'R4': 4, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 4, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 5, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02820: Output = NZ  Instr=C7 INC R3; regs={'R4': 5, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 5, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 6, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02821: Output = NZ  Instr=C7 INC R3; regs={'R4': 6, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 6, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 7, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02822: Output = NZ  Instr=C7 INC R3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02823: Output = Z  Instr=MUL NOP; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02824: Output = Z  Instr=D1 TDEC R4; regs={'R4': 8, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02825: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02826: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02827: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02828: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02829: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02830: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02831: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02832: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02833: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02834: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02835: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02836: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02837: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02838: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02839: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02840: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02841: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02842: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02843: Output = NZ  Instr=D2 INC R1; regs={'R4': 7, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 7, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02844: Output = Z  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02845: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02846: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02847: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02848: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02849: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02850: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02851: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02852: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02853: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02854: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02855: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02856: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02857: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02858: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02859: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02860: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02861: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02862: Output = NZ  Instr=D3 INC R0; regs={'R4': 7, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02863: Output = Z  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02864: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02865: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02866: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, 'x000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02867: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, 'x000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02868: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02869: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02870: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02871: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02872: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0x00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02873: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0x00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02874: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02875: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02876: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02877: Output = NZ  Instr=D6 SET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
02878: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '00x0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
02879: Output = NZ  Instr=D8 SET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '00x0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02880: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [3, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02881: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [3, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02882: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02883: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02884: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '001x000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02885: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '001x000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02886: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [4, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02887: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [4, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02888: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02889: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02890: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0010x00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02891: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0010x00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02892: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [5, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02893: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [5, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02894: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02895: Output = NZ  Instr=D6 SET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '00100x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
02896: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '00100x0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
02897: Output = NZ  Instr=D8 SET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '00100x0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0010010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02898: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [6, '0010010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02899: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [6, '0010010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02900: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0010010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02901: Output = NZ  Instr=D6 SET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0010010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '001001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0010010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0010010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
02902: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '001001x000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
02903: Output = NZ  Instr=D8 SET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '001001x000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02904: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [7, '0010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02905: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [7, '0010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02906: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02907: Output = NZ  Instr=D6 SET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
02908: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0010011x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
02909: Output = NZ  Instr=D8 SET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0010011x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02910: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [8, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02911: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [8, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02912: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02913: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '00100111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02914: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '00100111x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02915: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '00100111x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02916: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [9, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02917: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [9, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02918: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02919: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '001001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02920: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '001001110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02921: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '001001110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02922: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [10, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02923: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [10, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02924: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02925: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02926: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0010011100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02927: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0010011100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02928: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [11, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02929: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [11, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02930: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02931: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '00100111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02932: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '00100111000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02933: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '00100111000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02934: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [12, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02935: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [12, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02936: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02937: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '001001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02938: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '001001110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02939: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '001001110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02940: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [13, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02941: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [13, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02942: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02943: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02944: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0010011100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02945: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0010011100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02946: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [14, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02947: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [14, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02948: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02949: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '00100111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02950: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '00100111000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02951: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '00100111000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02952: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [15, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02953: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [15, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02954: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02955: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '001001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02956: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '001001110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02957: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '001001110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02958: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [16, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02959: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [16, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02960: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02961: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02962: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0010011100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02963: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0010011100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02964: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [17, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02965: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [17, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02966: Output = NZ  Instr=D5 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02967: Output = Z  Instr=D6 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '00100111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02968: Output = Z  Instr=D7 ADD B1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '00100111000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02969: Output = Z  Instr=D8 RESET T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '00100111000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02970: Output = NZ  Instr=D8A INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02971: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02972: Output = Z  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02973: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02974: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02975: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02976: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02977: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02978: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02979: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02980: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02981: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02982: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02983: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02984: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02985: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02986: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02987: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02988: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02989: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02990: Output = NZ  Instr=D9 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02991: Output = Z  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02992: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02993: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [16, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02994: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [15, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02995: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [14, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02996: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [13, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02997: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [12, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02998: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [11, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
02999: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03000: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [9, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03001: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [8, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03002: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [7, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03003: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [6, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03004: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [5, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03005: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [4, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03006: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [3, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03007: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [2, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03008: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [1, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03009: Output = NZ  Instr=D10 DEC T4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03010: Output = Z  Instr=D1 TDEC R4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03011: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03012: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03013: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03014: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03015: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03016: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03017: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03018: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03019: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03020: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03021: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03022: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03023: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03024: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03025: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03026: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03027: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03028: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03029: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03030: Output = Z  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03031: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03032: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03033: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03034: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03035: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03036: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03037: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03038: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03039: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03040: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03041: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03042: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03043: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03044: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03045: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03046: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03047: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03048: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03049: Output = Z  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03050: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03051: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03052: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, 'x010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03053: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, 'x010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03054: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [1, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03055: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [1, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03056: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03057: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03058: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0x10011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03059: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0x10011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03060: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [2, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03061: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [2, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03062: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03063: Output = NZ  Instr=D6 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03064: Output = NZ  Instr=D7 ADD B0; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '00x0011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03065: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '00x0011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03066: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [3, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03067: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [3, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03068: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03069: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03070: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '000x011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03071: Output = NZ  Instr=D8 SET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '000x011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0001011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03072: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [4, '0001011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03073: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [4, '0001011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03074: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0001011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03075: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0001011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0001011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03076: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0001x11100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03077: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0001x11100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0001011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03078: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [5, '0001011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03079: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [5, '0001011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03080: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0001011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03081: Output = NZ  Instr=D6 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0001011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '00100x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0001011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0001011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03082: Output = NZ  Instr=D7 ADD B0; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '00010x1100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03083: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '00010x1100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03084: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [6, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03085: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [6, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03086: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03087: Output = NZ  Instr=D6 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '001001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
03088: Output = NZ  Instr=D7 ADD B0; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '000100x100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
03089: Output = NZ  Instr=D8 SET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '000100x100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03090: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [7, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03091: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [7, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03092: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03093: Output = NZ  Instr=D6 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
03094: Output = NZ  Instr=D7 ADD B0; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0001001x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
03095: Output = NZ  Instr=D8 SET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0001001x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03096: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [8, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03097: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [8, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03098: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03099: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '00100111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0001001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03100: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '00010011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03101: Output = NZ  Instr=D8 SET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '00010011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03102: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [9, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03103: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [9, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03104: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03105: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '001001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03106: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '000100111x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03107: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '000100111x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03108: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [10, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03109: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [10, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03110: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03111: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03112: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0001001110x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03113: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0001001110x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03114: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [11, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03115: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [11, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03116: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03117: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '00100111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03118: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '00010011100x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03119: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '00010011100x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03120: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [12, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03121: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [12, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03122: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03123: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '001001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03124: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '000100111000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03125: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '000100111000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03126: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [13, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03127: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [13, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03128: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03129: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03130: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0001001110000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03131: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0001001110000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03132: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [14, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03133: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [14, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03134: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03135: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '00100111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03136: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '00010011100000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03137: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '00010011100000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03138: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [15, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03139: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [15, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03140: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03141: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '001001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03142: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '000100111000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03143: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '000100111000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03144: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [16, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03145: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [16, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03146: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03147: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03148: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0001001110000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03149: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0001001110000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03150: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [17, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03151: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [17, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03152: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03153: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '00100111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03154: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '00010011100000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03155: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '00010011100000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03156: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03157: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03158: Output = Z  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03159: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03160: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03161: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03162: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03163: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03164: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03165: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03166: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03167: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03168: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03169: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03170: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03171: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03172: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03173: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03174: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03175: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03176: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03177: Output = Z  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03178: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03179: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [16, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03180: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [15, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03181: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [14, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03182: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [13, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03183: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [12, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03184: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [11, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03185: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03186: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [9, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03187: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [8, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03188: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [7, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03189: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [6, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03190: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [5, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03191: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [4, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03192: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [3, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03193: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [2, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03194: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [1, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03195: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03196: Output = Z  Instr=D1 TDEC R4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03197: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03198: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03199: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03200: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03201: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03202: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03203: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03204: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03205: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03206: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03207: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03208: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03209: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03210: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03211: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03212: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03213: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03214: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03215: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03216: Output = Z  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03217: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03218: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03219: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03220: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03221: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03222: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03223: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03224: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03225: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03226: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03227: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03228: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03229: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03230: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03231: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03232: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03233: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03234: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03235: Output = Z  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03236: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03237: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03238: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, 'x001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03239: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, 'x001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03240: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [1, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03241: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [1, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03242: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03243: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03244: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0x01001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03245: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0x01001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03246: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [2, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03247: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [2, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03248: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03249: Output = NZ  Instr=D6 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03250: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '00x1001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03251: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '00x1001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03252: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [3, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03253: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [3, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03254: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03255: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03256: Output = NZ  Instr=D7 ADD B0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '001x001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03257: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '001x001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03258: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [4, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03259: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [4, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03260: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03261: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03262: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0011x01110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03263: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0011x01110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03264: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [5, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03265: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [5, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03266: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03267: Output = NZ  Instr=D6 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '00100x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0011001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03268: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '00110x1110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03269: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '00110x1110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0011011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03270: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [6, '0011011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03271: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [6, '0011011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03272: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0011011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03273: Output = NZ  Instr=D6 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0011011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '001001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0011011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0011011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03274: Output = NZ  Instr=D7 ADD B0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '001101x110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03275: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '001101x110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0011010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03276: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [7, '0011010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03277: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [7, '0011010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03278: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0011010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03279: Output = NZ  Instr=D6 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0011010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0011010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0011010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
03280: Output = NZ  Instr=D7 ADD B0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0011010x10000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
03281: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0011010x10000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0011010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03282: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [8, '0011010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03283: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [8, '0011010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03284: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0011010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03285: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0011010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '00100111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0011010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03286: Output = NZ  Instr=D7 ADD B0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '00110101x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03287: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '00110101x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0011010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03288: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [9, '0011010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03289: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [9, '0011010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03290: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0011010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03291: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0011010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '001001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0011010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03292: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '001101010x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03293: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '001101010x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03294: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [10, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03295: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [10, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03296: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03297: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03298: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0011010101x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03299: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0011010101x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03300: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [11, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03301: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [11, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03302: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03303: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '00100111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03304: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '00110101010x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03305: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '00110101010x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03306: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [12, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03307: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [12, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03308: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03309: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '001001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03310: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '001101010100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03311: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '001101010100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03312: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [13, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03313: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [13, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03314: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03315: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03316: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0011010101000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03317: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0011010101000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03318: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [14, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03319: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [14, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03320: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03321: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '00100111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03322: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '00110101010000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03323: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '00110101010000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03324: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [15, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03325: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [15, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03326: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03327: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '001001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03328: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '001101010100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03329: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '001101010100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03330: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [16, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03331: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [16, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03332: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03333: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03334: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0011010101000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03335: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0011010101000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03336: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [17, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03337: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [17, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03338: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03339: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '00100111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03340: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '00110101010000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03341: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '00110101010000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03342: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03343: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03344: Output = Z  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03345: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03346: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03347: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03348: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03349: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03350: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03351: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03352: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03353: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03354: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03355: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03356: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03357: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03358: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03359: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03360: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03361: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03362: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03363: Output = Z  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03364: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03365: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [16, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03366: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [15, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03367: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [14, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03368: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [13, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03369: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [12, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03370: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [11, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03371: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03372: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [9, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03373: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [8, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03374: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [7, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03375: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [6, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03376: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [5, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03377: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [4, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03378: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [3, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03379: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [2, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03380: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [1, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03381: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03382: Output = Z  Instr=D1 TDEC R4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03383: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03384: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03385: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03386: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03387: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03388: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03389: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03390: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03391: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03392: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03393: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03394: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03395: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03396: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03397: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03398: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03399: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03400: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03401: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03402: Output = Z  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03403: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03404: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03405: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03406: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03407: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03408: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03409: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03410: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03411: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03412: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03413: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03414: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03415: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03416: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03417: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03418: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03419: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03420: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03421: Output = Z  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03422: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03423: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03424: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, 'x011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03425: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, 'x011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03426: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [1, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03427: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [1, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03428: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03429: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03430: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0x11010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03431: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0x11010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03432: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [2, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03433: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [2, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03434: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03435: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03436: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '00x1010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03437: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '00x1010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03438: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [3, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03439: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [3, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03440: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03441: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03442: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '000x010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03443: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '000x010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03444: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [4, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03445: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [4, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03446: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03447: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03448: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0000x10101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03449: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0000x10101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0000110101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03450: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [5, '0000110101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03451: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [5, '0000110101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03452: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0000110101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03453: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0000110101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '00100x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0000110101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0000110101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03454: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '00001x0101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03455: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '00001x0101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03456: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [6, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03457: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [6, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03458: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03459: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '001001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
03460: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '000010x101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
03461: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '000010x101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03462: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [7, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03463: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [7, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03464: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03465: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
03466: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000100x01000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
03467: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000100x01000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03468: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [8, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03469: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [8, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03470: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03471: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '00100111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03472: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '00001001x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03473: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '00001001x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03474: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [9, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03475: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [9, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03476: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03477: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '001001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03478: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '000010011x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03479: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '000010011x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03480: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [10, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03481: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [10, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03482: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03483: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03484: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0000100111x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03485: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0000100111x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03486: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [11, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03487: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [11, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03488: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03489: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '00100111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03490: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '00001001110x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03491: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '00001001110x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03492: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [12, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03493: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [12, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03494: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03495: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '001001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03496: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '000010011100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03497: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '000010011100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03498: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [13, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03499: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [13, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03500: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03501: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03502: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0000100111000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03503: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0000100111000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03504: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [14, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03505: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [14, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03506: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03507: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '00100111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03508: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '00001001110000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03509: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '00001001110000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03510: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [15, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03511: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [15, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03512: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03513: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '001001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03514: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '000010011100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03515: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '000010011100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03516: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [16, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03517: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [16, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03518: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03519: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03520: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0000100111000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03521: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0000100111000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03522: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [17, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03523: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [17, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03524: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03525: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '00100111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03526: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '00001001110000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03527: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '00001001110000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03528: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03529: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03530: Output = Z  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03531: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03532: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03533: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03534: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03535: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03536: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03537: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03538: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03539: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03540: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03541: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03542: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03543: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03544: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03545: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03546: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03547: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03548: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03549: Output = Z  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03550: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03551: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [16, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03552: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [15, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03553: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [14, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03554: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [13, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03555: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [12, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03556: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [11, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03557: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03558: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [9, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03559: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [8, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03560: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [7, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03561: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [6, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03562: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [5, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03563: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [4, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03564: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [3, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03565: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [2, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03566: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [1, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03567: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03568: Output = Z  Instr=D1 TDEC R4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03569: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03570: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03571: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03572: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03573: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03574: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03575: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03576: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03577: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03578: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03579: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03580: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03581: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03582: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03583: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03584: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03585: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03586: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03587: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03588: Output = Z  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03589: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03590: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03591: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03592: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03593: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03594: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03595: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03596: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03597: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03598: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03599: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03600: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03601: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03602: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03603: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03604: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03605: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03606: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03607: Output = Z  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03608: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03609: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03610: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, 'x000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03611: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, 'x000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03612: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [1, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03613: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [1, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03614: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03615: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03616: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0x00100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03617: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0x00100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03618: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [2, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03619: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [2, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03620: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03621: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0000100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03622: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '00x0100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03623: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '00x0100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03624: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [3, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03625: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [3, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03626: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03627: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03628: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '001x100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03629: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '001x100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03630: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [4, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03631: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [4, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03632: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03633: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03634: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0010x00111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03635: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0010x00111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03636: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [5, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03637: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [5, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03638: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03639: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '00100x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0010100111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03640: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '00101x0111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03641: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '00101x0111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0010110111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03642: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [6, '0010110111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03643: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [6, '0010110111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03644: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0010110111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03645: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0010110111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '001001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0010110111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0010110111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03646: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '001011x111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03647: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '001011x111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0010111111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03648: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [7, '0010111111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03649: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [7, '0010111111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03650: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0010111111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03651: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0010111111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0010111111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0010111111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03652: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0010111x11000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03653: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0010111x11000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0010111011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03654: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [8, '0010111011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03655: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [8, '0010111011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03656: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0010111011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03657: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0010111011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '00100111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0010111011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03658: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '00101110x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03659: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '00101110x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0010111001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03660: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [9, '0010111001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03661: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [9, '0010111001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03662: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0010111001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03663: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0010111001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '001001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0010111001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03664: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '001011100x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03665: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '001011100x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0010111000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03666: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [10, '0010111000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03667: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [10, '0010111000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03668: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0010111000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03669: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0010111000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0010111000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03670: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0010111000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03671: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0010111000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03672: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [11, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03673: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [11, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03674: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03675: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '00100111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03676: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '00101110001x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03677: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '00101110001x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03678: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [12, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03679: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [12, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03680: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03681: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '001001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03682: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '001011100010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03683: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '001011100010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03684: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [13, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03685: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [13, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03686: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03687: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03688: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0010111000100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03689: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0010111000100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03690: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [14, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03691: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [14, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03692: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03693: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '00100111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03694: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '00101110001000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03695: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '00101110001000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03696: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [15, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03697: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [15, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03698: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03699: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '001001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03700: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '001011100010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03701: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '001011100010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03702: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [16, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03703: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [16, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03704: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03705: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03706: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0010111000100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03707: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0010111000100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03708: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [17, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03709: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [17, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03710: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03711: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '00100111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03712: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '00101110001000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03713: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '00101110001000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03714: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03715: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03716: Output = Z  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03717: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03718: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03719: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03720: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03721: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03722: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03723: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03724: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03725: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03726: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03727: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03728: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03729: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03730: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03731: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03732: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03733: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03734: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03735: Output = Z  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03736: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03737: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [16, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03738: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [15, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03739: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [14, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03740: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [13, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03741: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [12, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03742: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [11, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03743: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03744: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [9, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03745: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [8, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03746: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [7, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03747: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [6, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03748: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [5, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03749: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [4, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03750: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [3, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03751: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [2, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03752: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [1, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03753: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03754: Output = Z  Instr=D1 TDEC R4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03755: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03756: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03757: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03758: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03759: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03760: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03761: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03762: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03763: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03764: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03765: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03766: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03767: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03768: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03769: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03770: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03771: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03772: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03773: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03774: Output = Z  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03775: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03776: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03777: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03778: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03779: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03780: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03781: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03782: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03783: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03784: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03785: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03786: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03787: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03788: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03789: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03790: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03791: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03792: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03793: Output = Z  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03794: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03795: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03796: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, 'x010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03797: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, 'x010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03798: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [1, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03799: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [1, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03800: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03801: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03802: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0x10111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03803: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0x10111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03804: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [2, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03805: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [2, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03806: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03807: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0010111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03808: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '00x0111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03809: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '00x0111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0000111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03810: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [3, '0000111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03811: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [3, '0000111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03812: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0000111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03813: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0000111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0000111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03814: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '000x111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03815: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '000x111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03816: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [4, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03817: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [4, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03818: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03819: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03820: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0001x11000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03821: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0001x11000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03822: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [5, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03823: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [5, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03824: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03825: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '00100x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0001111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03826: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '00011x1000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03827: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '00011x1000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03828: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [6, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03829: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [6, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03830: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03831: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '001001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
03832: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '000110x000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
03833: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '000110x000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03834: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [7, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03835: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [7, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03836: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03837: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
03838: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0001101x00100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
03839: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0001101x00100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03840: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [8, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03841: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [8, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03842: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03843: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '00100111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0001101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03844: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '00011010x0100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
03845: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '00011010x0100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03846: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [9, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03847: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [9, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03848: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03849: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '001001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03850: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '000110101x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03851: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '000110101x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03852: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [10, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03853: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [10, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03854: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03855: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03856: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0001101010x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03857: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0001101010x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03858: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [11, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03859: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [11, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03860: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03861: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '00100111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03862: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '00011010101x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03863: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '00011010101x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03864: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [12, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03865: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [12, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03866: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03867: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '001001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03868: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '000110101010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03869: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '000110101010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03870: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [13, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03871: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [13, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03872: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03873: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03874: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0001101010100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03875: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0001101010100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03876: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [14, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03877: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [14, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03878: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03879: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '00100111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03880: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '00011010101000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03881: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '00011010101000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03882: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [15, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03883: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [15, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03884: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03885: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '001001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03886: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '000110101010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03887: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '000110101010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03888: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [16, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03889: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [16, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03890: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03891: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03892: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0001101010100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03893: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0001101010100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03894: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [17, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03895: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [17, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03896: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03897: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '00100111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03898: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '00011010101000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03899: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '00011010101000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03900: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03901: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03902: Output = Z  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03903: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03904: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03905: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03906: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03907: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03908: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03909: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03910: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03911: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03912: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03913: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03914: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03915: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03916: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03917: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03918: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03919: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03920: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03921: Output = Z  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03922: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03923: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [16, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03924: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [15, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03925: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [14, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03926: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [13, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03927: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [12, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03928: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [11, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03929: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03930: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [9, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03931: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [8, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03932: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [7, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03933: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [6, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03934: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [5, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03935: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [4, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03936: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [3, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03937: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [2, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03938: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [1, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03939: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03940: Output = Z  Instr=D1 TDEC R4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03941: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03942: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03943: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03944: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03945: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03946: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03947: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03948: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03949: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03950: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03951: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03952: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03953: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03954: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03955: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03956: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03957: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03958: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03959: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03960: Output = Z  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03961: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03962: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03963: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03964: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03965: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03966: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03967: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03968: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03969: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03970: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03971: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03972: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03973: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03974: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03975: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03976: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03977: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03978: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03979: Output = Z  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03980: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03981: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03982: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, 'x001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03983: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, 'x001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03984: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [1, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03985: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [1, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03986: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03987: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03988: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0x01101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03989: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0x01101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03990: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [2, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03991: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [2, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03992: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03993: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0001101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03994: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '00x1101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
03995: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '00x1101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03996: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [3, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03997: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [3, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03998: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
03999: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04000: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '001x101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04001: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '001x101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04002: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [4, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04003: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [4, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04004: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04005: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04006: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0011x01010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04007: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0011x01010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04008: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [5, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04009: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [5, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04010: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04011: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '00100x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0011101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
04012: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '00111x1010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
04013: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '00111x1010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0011111010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04014: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [6, '0011111010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04015: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [6, '0011111010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04016: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0011111010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04017: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0011111010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '001001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0011111010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0011111010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
04018: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '001111x010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
04019: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '001111x010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0011110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04020: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [7, '0011110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04021: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [7, '0011110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04022: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0011110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04023: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0011110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0011110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0011110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
04024: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0011110x10100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
04025: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0011110x10100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0011110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04026: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [8, '0011110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04027: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [8, '0011110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04028: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0011110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04029: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0011110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '00100111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0011110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04030: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '00111100x0100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04031: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '00111100x0100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0011110000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04032: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [9, '0011110000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04033: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [9, '0011110000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04034: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0011110000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04035: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0011110000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '001001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0011110000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04036: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '001111000x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04037: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '001111000x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04038: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [10, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04039: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [10, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04040: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04041: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04042: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0011110001x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04043: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0011110001x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04044: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [11, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04045: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [11, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04046: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04047: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '00100111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04048: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '00111100011x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04049: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '00111100011x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04050: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [12, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04051: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [12, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04052: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04053: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '001001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04054: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '001111000110x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04055: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '001111000110x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04056: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [13, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04057: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [13, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04058: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04059: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04060: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0011110001100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04061: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0011110001100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04062: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [14, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04063: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [14, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04064: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04065: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '00100111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04066: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '00111100011000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04067: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '00111100011000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04068: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [15, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04069: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [15, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04070: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04071: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '001001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04072: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '001111000110000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04073: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '001111000110000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04074: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [16, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04075: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [16, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04076: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04077: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04078: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0011110001100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04079: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0011110001100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04080: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [17, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04081: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [17, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04082: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04083: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '00100111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04084: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '00111100011000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04085: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '00111100011000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04086: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04087: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04088: Output = Z  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04089: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04090: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04091: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04092: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04093: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04094: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04095: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04096: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04097: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04098: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04099: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04100: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04101: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04102: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04103: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04104: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04105: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04106: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04107: Output = Z  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04108: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04109: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [16, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04110: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [15, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04111: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [14, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04112: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [13, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04113: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [12, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04114: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [11, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04115: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04116: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [9, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04117: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [8, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04118: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [7, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04119: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [6, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04120: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [5, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04121: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [4, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04122: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [3, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04123: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [2, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04124: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [1, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04125: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04126: Output = Z  Instr=D1 TDEC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04127: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04128: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04129: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04130: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04131: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04132: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04133: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04134: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04135: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04136: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04137: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04138: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04139: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04140: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04141: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04142: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04143: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04144: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04145: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04146: Output = Z  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04147: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04148: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04149: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04150: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04151: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04152: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04153: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04154: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04155: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04156: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04157: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04158: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04159: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04160: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04161: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04162: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04163: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04164: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04165: Output = Z  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04166: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04167: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04168: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, 'x011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04169: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, 'x011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04170: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [1, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04171: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [1, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04172: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04173: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04174: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0x11110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04175: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0x11110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04176: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [2, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04177: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [2, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04178: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04179: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0011110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
04180: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '00x1110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
04181: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '00x1110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0001110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04182: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [3, '0001110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04183: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [3, '0001110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04184: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0001110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04185: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0001110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0001110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04186: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '000x110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04187: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '000x110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0000110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04188: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [4, '0000110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04189: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [4, '0000110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04190: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0000110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04191: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0000110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0000110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04192: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0000x10001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04193: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0000x10001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04194: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [5, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04195: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [5, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04196: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04197: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '00100x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
04198: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '00000x0001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
04199: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '00000x0001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04200: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [6, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04201: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [6, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04202: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04203: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '001001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
04204: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '000001x001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
04205: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '000001x001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04206: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [7, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04207: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [7, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04208: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04209: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
04210: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000010x01100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
04211: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000010x01100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04212: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [8, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04213: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [8, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04214: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04215: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '00100111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04216: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '00000100x1100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
04217: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '00000100x1100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04218: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [9, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04219: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [9, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04220: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04221: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '001001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04222: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '000001001x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04223: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '000001001x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04224: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04225: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04226: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04227: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04228: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0000010011x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04229: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0000010011x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04230: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [11, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04231: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [11, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04232: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04233: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '00100111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04234: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '00000100111x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04235: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '00000100111x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04236: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [12, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04237: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [12, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04238: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04239: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '001001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04240: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '000001001110x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04241: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '000001001110x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04242: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [13, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04243: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [13, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04244: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04245: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04246: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0000010011100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04247: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0000010011100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04248: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [14, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04249: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [14, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04250: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04251: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '00100111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04252: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '00000100111000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04253: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '00000100111000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04254: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [15, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04255: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [15, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04256: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04257: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '001001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04258: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '000001001110000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04259: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '000001001110000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04260: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [16, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04261: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [16, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04262: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04263: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04264: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0000010011100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04265: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0000010011100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04266: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [17, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04267: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [17, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04268: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04269: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '00100111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04270: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '00000100111000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04271: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '00000100111000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04272: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04273: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04274: Output = Z  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04275: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04276: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04277: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04278: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04279: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04280: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04281: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04282: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04283: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04284: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04285: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04286: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04287: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04288: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04289: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04290: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04291: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04292: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04293: Output = Z  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04294: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04295: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [16, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04296: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [15, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04297: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [14, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04298: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [13, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04299: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [12, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04300: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [11, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04301: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04302: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [9, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04303: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [8, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04304: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [7, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04305: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [6, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04306: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [5, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04307: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [4, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04308: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [3, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04309: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [2, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04310: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [1, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04311: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04312: Output = Z  Instr=D1 TDEC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04313: Output = Z  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04314: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04315: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04316: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04317: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04318: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04319: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04320: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04321: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04322: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04323: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04324: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04325: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04326: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04327: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04328: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04329: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04330: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04331: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04332: Output = Z  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04333: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04334: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04335: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04336: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04337: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04338: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04339: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04340: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04341: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04342: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04343: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04344: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04345: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04346: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04347: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04348: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04349: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04350: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04351: Output = Z  Instr=COMP NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04352: Output = Z  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04353: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04354: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04355: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 8, 'T4': [1, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04356: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04357: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [1, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04358: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 8, 'T4': [2, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04359: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04360: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [2, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04361: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 8, 'T4': [3, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04362: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04363: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [3, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04364: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 8, 'T4': [4, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04365: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04366: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [4, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04367: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 8, 'T4': [5, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04368: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04369: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [5, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04370: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 8, 'T4': [6, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04371: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04372: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [6, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04373: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 8, 'T4': [7, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04374: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04375: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [7, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04376: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 8, 'T4': [8, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04377: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04378: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [8, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04379: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 8, 'T4': [9, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04380: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04381: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [9, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04382: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04383: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04384: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04385: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 8, 'T4': [11, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04386: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04387: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [11, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04388: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 8, 'T4': [12, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04389: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04390: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [12, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04391: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 8, 'T4': [13, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04392: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04393: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [13, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04394: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 8, 'T4': [14, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04395: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04396: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [14, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04397: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 8, 'T4': [15, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04398: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04399: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [15, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04400: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 8, 'T4': [16, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04401: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04402: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [16, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04403: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 8, 'T4': [17, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04404: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04405: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04406: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04407: Output = Z  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04408: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '000010011000000000x'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04409: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '000001001110000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [18, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04410: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04411: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04412: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '00001001100000000x0'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04413: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '00000100111000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [17, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04414: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [16, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04415: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [16, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04416: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [16, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000x00'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [16, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04417: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [16, '0000010011100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [16, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04418: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [15, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04419: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [15, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04420: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [15, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '000010011000000x000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [15, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04421: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [15, '000001001110000x000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [15, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04422: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [14, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04423: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [14, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04424: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [14, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '00001001100000x0000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [14, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04425: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [14, '00000100111000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [14, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04426: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [13, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04427: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [13, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04428: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [13, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000x00000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [13, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04429: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [13, '0000010011100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [13, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04430: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [12, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04431: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [12, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04432: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [12, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '000010011000x000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [12, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04433: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [12, '000001001110x000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [12, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04434: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [11, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04435: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [11, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04436: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [11, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '00001001100x0000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [11, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04437: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [11, '00000100111x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [11, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04438: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04439: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04440: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110x00000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04441: Output = NZ  Instr=E9 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000010011x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04442: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04443: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04444: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04445: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04446: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04447: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04448: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04449: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04450: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04451: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04452: Output = Z  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [10, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04453: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [9, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04454: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [8, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04455: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [7, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04456: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [6, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04457: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [5, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04458: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [4, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04459: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [3, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04460: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [2, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04461: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [1, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04462: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04463: Output = Z  Instr=E11 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 8, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04464: Output = NZ  Instr=EVL NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04465: Output = Z  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04466: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04467: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04468: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04469: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04470: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04471: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04472: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04473: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04474: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04475: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04476: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04477: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04478: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04479: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04480: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04481: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04482: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04483: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04484: Output = Z  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04485: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04486: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04487: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04488: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04489: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04490: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04491: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04492: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04493: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04494: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04495: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04496: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04497: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04498: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04499: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04500: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04501: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04502: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04503: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04504: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04505: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, 'x000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04506: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [1, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04507: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04508: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0x00010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04509: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [2, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04510: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04511: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '00x0010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04512: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [3, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04513: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04514: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '000x010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04515: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [4, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04516: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04517: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0000x10011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04518: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [5, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04519: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '0000010011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04520: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '00000x0011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '0000000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04521: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [6, '0000000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04522: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '0000000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04523: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '000000x011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '0000000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04524: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [7, '0000000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04525: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0000000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04526: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0000000x11100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0000000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04527: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [8, '0000000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04528: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '0000000011100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04529: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '00000000x1100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '0000000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04530: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [9, '0000000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04531: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '0000000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04532: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '000000000x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04533: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [10, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04534: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04535: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0000000000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04536: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04537: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04538: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '00000000000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04539: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04540: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04541: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '000000000000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04542: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04543: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04544: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0000000000000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04545: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04546: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04547: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '00000000000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04548: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04549: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04550: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '000000000000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04551: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04552: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04553: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0000000000000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04554: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04555: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04556: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '00000000000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04557: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04558: Output = Z  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04559: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04560: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04561: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04562: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04563: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04564: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04565: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04566: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04567: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [9, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04568: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [8, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04569: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [7, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04570: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [6, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04571: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [5, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04572: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [4, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04573: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [3, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04574: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04575: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04576: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04577: Output = Z  Instr=B5 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04578: Output = Z  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04579: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04580: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04581: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04582: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04583: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04584: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04585: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04586: Output = Z  Instr=B7 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04587: Output = NZ  Instr=B7 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04588: Output = NZ  Instr=B7 INC R3; regs={'R4': 1, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 1, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04589: Output = NZ  Instr=B7 INC R3; regs={'R4': 2, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 2, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04590: Output = NZ  Instr=B7 INC R3; regs={'R4': 3, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 3, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 4, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04591: Output = NZ  Instr=B7 INC R3; regs={'R4': 4, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 4, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 5, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04592: Output = NZ  Instr=B7 INC R3; regs={'R4': 5, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 5, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 6, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04593: Output = NZ  Instr=B7 INC R3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04594: Output = Z  Instr=B8 NOP; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04595: Output = Z  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04596: Output = NZ  Instr=B9 INC R1; regs={'R4': 7, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04597: Output = NZ  Instr=B9 INC R1; regs={'R4': 7, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04598: Output = NZ  Instr=B9 INC R1; regs={'R4': 7, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04599: Output = NZ  Instr=B9 INC R1; regs={'R4': 7, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04600: Output = NZ  Instr=B9 INC R1; regs={'R4': 7, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04601: Output = NZ  Instr=B9 INC R1; regs={'R4': 7, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04602: Output = NZ  Instr=B9 INC R1; regs={'R4': 7, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04603: Output = NZ  Instr=B9 INC R1; regs={'R4': 7, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04604: Output = NZ  Instr=B9 INC R1; regs={'R4': 7, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04605: Output = NZ  Instr=B9 INC R1; regs={'R4': 7, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04606: Output = NZ  Instr=B9 INC R1; regs={'R4': 7, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04607: Output = NZ  Instr=B9 INC R1; regs={'R4': 7, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04608: Output = NZ  Instr=B9 INC R1; regs={'R4': 7, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04609: Output = NZ  Instr=B9 INC R1; regs={'R4': 7, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04610: Output = NZ  Instr=B9 INC R1; regs={'R4': 7, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04611: Output = NZ  Instr=B9 INC R1; regs={'R4': 7, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04612: Output = NZ  Instr=B9 INC R1; regs={'R4': 7, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04613: Output = NZ  Instr=B9 INC R1; regs={'R4': 7, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 7, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04614: Output = Z  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04615: Output = NZ  Instr=B10 INC R0; regs={'R4': 7, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 7, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04616: Output = NZ  Instr=B10 INC R0; regs={'R4': 7, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 7, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04617: Output = NZ  Instr=B10 INC R0; regs={'R4': 7, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 7, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04618: Output = NZ  Instr=B10 INC R0; regs={'R4': 7, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 7, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04619: Output = NZ  Instr=B10 INC R0; regs={'R4': 7, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 7, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04620: Output = NZ  Instr=B10 INC R0; regs={'R4': 7, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 7, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04621: Output = NZ  Instr=B10 INC R0; regs={'R4': 7, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 7, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04622: Output = NZ  Instr=B10 INC R0; regs={'R4': 7, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 7, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04623: Output = NZ  Instr=B10 INC R0; regs={'R4': 7, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 7, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04624: Output = NZ  Instr=B10 INC R0; regs={'R4': 7, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 7, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04625: Output = NZ  Instr=B10 INC R0; regs={'R4': 7, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 7, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04626: Output = NZ  Instr=B10 INC R0; regs={'R4': 7, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 7, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04627: Output = NZ  Instr=B10 INC R0; regs={'R4': 7, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 7, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04628: Output = NZ  Instr=B10 INC R0; regs={'R4': 7, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 7, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04629: Output = NZ  Instr=B10 INC R0; regs={'R4': 7, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 7, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04630: Output = NZ  Instr=B10 INC R0; regs={'R4': 7, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 7, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04631: Output = NZ  Instr=B10 INC R0; regs={'R4': 7, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 7, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04632: Output = NZ  Instr=B10 INC R0; regs={'R4': 7, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04633: Output = Z  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04634: Output = NZ  Instr=B12 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04635: Output = Z  Instr=B13 READ T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04636: Output = Z  Instr=B14 RESET T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, 'x011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04637: Output = NZ  Instr=B15 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [0, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04638: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04639: Output = NZ  Instr=B12 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04640: Output = Z  Instr=B13 READ T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04641: Output = Z  Instr=B14 RESET T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [1, '0x11101100000000000'], 'T3': [1, '0x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0x10011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04642: Output = NZ  Instr=B15 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [1, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04643: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04644: Output = NZ  Instr=B12 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04645: Output = NZ  Instr=B13 READ T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04646: Output = NZ  Instr=B14 SET T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [2, '00x1101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04647: Output = NZ  Instr=B15 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04648: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04649: Output = NZ  Instr=B12 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04650: Output = Z  Instr=B13 READ T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04651: Output = NZ  Instr=B14 SET T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [3, '001x101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04652: Output = NZ  Instr=B15 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [3, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04653: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04654: Output = NZ  Instr=B12 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04655: Output = Z  Instr=B13 READ T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04656: Output = NZ  Instr=B14 SET T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011x01100000000000'], 'T3': [4, '0011x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04657: Output = NZ  Instr=B15 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [4, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04658: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04659: Output = NZ  Instr=B12 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04660: Output = NZ  Instr=B13 READ T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04661: Output = Z  Instr=B14 RESET T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [5, '00111x1100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04662: Output = NZ  Instr=B15 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04663: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04664: Output = NZ  Instr=B12 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04665: Output = NZ  Instr=B13 READ T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04666: Output = NZ  Instr=B14 SET T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [6, '001110x100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04667: Output = NZ  Instr=B15 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04668: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04669: Output = NZ  Instr=B12 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04670: Output = NZ  Instr=B13 READ T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04671: Output = NZ  Instr=B14 SET T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101x00000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04672: Output = NZ  Instr=B15 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04673: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04674: Output = NZ  Instr=B12 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04675: Output = Z  Instr=B13 READ T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04676: Output = Z  Instr=B14 RESET T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [8, '00111011x0000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04677: Output = NZ  Instr=B15 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04678: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04679: Output = NZ  Instr=B12 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04680: Output = Z  Instr=B13 READ T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04681: Output = Z  Instr=B14 RESET T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [9, '001110110x000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04682: Output = NZ  Instr=B15 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04683: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04684: Output = NZ  Instr=B12 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04685: Output = Z  Instr=B13 READ T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04686: Output = Z  Instr=B14 RESET T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100x00000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04687: Output = NZ  Instr=B15 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04688: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04689: Output = NZ  Instr=B12 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04690: Output = Z  Instr=B13 READ T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04691: Output = Z  Instr=B14 RESET T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [11, '00111011000x0000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04692: Output = NZ  Instr=B15 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04693: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04694: Output = NZ  Instr=B12 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04695: Output = Z  Instr=B13 READ T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04696: Output = Z  Instr=B14 RESET T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [12, '001110110000x000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04697: Output = NZ  Instr=B15 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04698: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04699: Output = NZ  Instr=B12 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04700: Output = Z  Instr=B13 READ T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04701: Output = Z  Instr=B14 RESET T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000x00000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04702: Output = NZ  Instr=B15 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04703: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04704: Output = NZ  Instr=B12 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04705: Output = Z  Instr=B13 READ T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04706: Output = Z  Instr=B14 RESET T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [14, '00111011000000x0000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04707: Output = NZ  Instr=B15 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04708: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04709: Output = NZ  Instr=B12 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04710: Output = Z  Instr=B13 READ T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04711: Output = Z  Instr=B14 RESET T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [15, '001110110000000x000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04712: Output = NZ  Instr=B15 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04713: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04714: Output = NZ  Instr=B12 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04715: Output = Z  Instr=B13 READ T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04716: Output = Z  Instr=B14 RESET T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000x00'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04717: Output = NZ  Instr=B15 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04718: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04719: Output = NZ  Instr=B12 READ T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04720: Output = Z  Instr=B13 READ T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04721: Output = Z  Instr=B14 RESET T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [17, '00111011000000000x0'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04722: Output = NZ  Instr=B15 INC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04723: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04724: Output = Z  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04725: Output = NZ  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04726: Output = NZ  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04727: Output = NZ  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04728: Output = NZ  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04729: Output = NZ  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04730: Output = NZ  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04731: Output = NZ  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04732: Output = NZ  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04733: Output = NZ  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04734: Output = NZ  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04735: Output = NZ  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04736: Output = NZ  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04737: Output = NZ  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04738: Output = NZ  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04739: Output = NZ  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04740: Output = NZ  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04741: Output = NZ  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04742: Output = NZ  Instr=B16 DEC T2; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04743: Output = Z  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04744: Output = NZ  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04745: Output = NZ  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04746: Output = NZ  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04747: Output = NZ  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04748: Output = NZ  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04749: Output = NZ  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04750: Output = NZ  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04751: Output = NZ  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04752: Output = NZ  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04753: Output = NZ  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04754: Output = NZ  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04755: Output = NZ  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04756: Output = NZ  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04757: Output = NZ  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04758: Output = NZ  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04759: Output = NZ  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04760: Output = NZ  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04761: Output = NZ  Instr=B17 DEC T3; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04762: Output = Z  Instr=ADD NOP; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04763: Output = Z  Instr=C1 TDEC R4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04764: Output = NZ  Instr=C2 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04765: Output = Z  Instr=C4 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04766: Output = Z  Instr=C1 TDEC R4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04767: Output = NZ  Instr=C2 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04768: Output = NZ  Instr=C3 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04769: Output = NZ  Instr=C2 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04770: Output = Z  Instr=C4 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04771: Output = NZ  Instr=C4 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04772: Output = Z  Instr=C1 TDEC R4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04773: Output = NZ  Instr=C2 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04774: Output = Z  Instr=C4 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04775: Output = Z  Instr=C1 TDEC R4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04776: Output = NZ  Instr=C2 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04777: Output = NZ  Instr=C3 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04778: Output = NZ  Instr=C2 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04779: Output = NZ  Instr=C3 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04780: Output = NZ  Instr=C2 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04781: Output = NZ  Instr=C3 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x1101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0001101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04782: Output = NZ  Instr=C2 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0001101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04783: Output = NZ  Instr=C3 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '000x101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04784: Output = NZ  Instr=C2 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04785: Output = NZ  Instr=C3 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000x01100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000001100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04786: Output = NZ  Instr=C2 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000001100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04787: Output = Z  Instr=C4 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '00000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04788: Output = NZ  Instr=C4 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04789: Output = NZ  Instr=C4 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04790: Output = NZ  Instr=C4 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04791: Output = NZ  Instr=C4 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04792: Output = NZ  Instr=C4 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04793: Output = Z  Instr=C1 TDEC R4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04794: Output = NZ  Instr=C2 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04795: Output = Z  Instr=C4 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04796: Output = Z  Instr=C1 TDEC R4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04797: Output = NZ  Instr=C2 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04798: Output = NZ  Instr=C3 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04799: Output = NZ  Instr=C2 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04800: Output = Z  Instr=C4 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04801: Output = NZ  Instr=C4 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04802: Output = Z  Instr=C1 TDEC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04803: Output = NZ  Instr=C2 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04804: Output = Z  Instr=C4 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04805: Output = Z  Instr=C1 TDEC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04806: Output = Z  Instr=C5 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04807: Output = Z  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04808: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04809: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04810: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04811: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04812: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04813: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04814: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04815: Output = Z  Instr=C7 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 7, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04816: Output = NZ  Instr=C7 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04817: Output = NZ  Instr=C7 INC R3; regs={'R4': 1, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 1, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04818: Output = NZ  Instr=C7 INC R3; regs={'R4': 2, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 2, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04819: Output = NZ  Instr=C7 INC R3; regs={'R4': 3, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 3, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 4, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04820: Output = NZ  Instr=C7 INC R3; regs={'R4': 4, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 4, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 5, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04821: Output = NZ  Instr=C7 INC R3; regs={'R4': 5, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 5, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 6, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04822: Output = NZ  Instr=C7 INC R3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04823: Output = Z  Instr=MUL NOP; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04824: Output = Z  Instr=D1 TDEC R4; regs={'R4': 7, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04825: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04826: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04827: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04828: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04829: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04830: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04831: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04832: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04833: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04834: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04835: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04836: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04837: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04838: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04839: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04840: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04841: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04842: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04843: Output = NZ  Instr=D2 INC R1; regs={'R4': 6, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 6, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04844: Output = Z  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04845: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04846: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04847: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04848: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04849: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04850: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04851: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04852: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04853: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04854: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04855: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04856: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04857: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04858: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04859: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04860: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04861: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04862: Output = NZ  Instr=D3 INC R0; regs={'R4': 6, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04863: Output = Z  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04864: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04865: Output = NZ  Instr=D6 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
04866: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, 'x000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
04867: Output = NZ  Instr=D8 SET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, 'x000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04868: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04869: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04870: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04871: Output = NZ  Instr=D6 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
04872: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1x00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
04873: Output = NZ  Instr=D8 SET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1x00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04874: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [2, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04875: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [2, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04876: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04877: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '11x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04878: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '11x0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04879: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '11x0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04880: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [3, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04881: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [3, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04882: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04883: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '110x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04884: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '110x000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04885: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '110x000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04886: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [4, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04887: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [4, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04888: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04889: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04890: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1100x00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04891: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1100x00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04892: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [5, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04893: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [5, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04894: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04895: Output = NZ  Instr=D6 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '11000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
04896: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '11000x0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
04897: Output = NZ  Instr=D8 SET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '11000x0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1100010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04898: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [6, '1100010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04899: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [6, '1100010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04900: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1100010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04901: Output = NZ  Instr=D6 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1100010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '110001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1100010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1100010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
04902: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '110001x000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
04903: Output = NZ  Instr=D8 SET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '110001x000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1100011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04904: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [7, '1100011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04905: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [7, '1100011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04906: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1100011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04907: Output = NZ  Instr=D6 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1100011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1100011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1100011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
04908: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1100011x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
04909: Output = NZ  Instr=D8 SET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1100011x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04910: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [8, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04911: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [8, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04912: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04913: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '11000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04914: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '11000111x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04915: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '11000111x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04916: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [9, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04917: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [9, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04918: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04919: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '110001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04920: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '110001110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04921: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '110001110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04922: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [10, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04923: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [10, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04924: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04925: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04926: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1100011100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04927: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1100011100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04928: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [11, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04929: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [11, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04930: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04931: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '11000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04932: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '11000111000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04933: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '11000111000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04934: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [12, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04935: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [12, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04936: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04937: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '110001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04938: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '110001110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04939: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '110001110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04940: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [13, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04941: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [13, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04942: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04943: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04944: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1100011100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04945: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1100011100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04946: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [14, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04947: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [14, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04948: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04949: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '11000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04950: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '11000111000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04951: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '11000111000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04952: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [15, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04953: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [15, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04954: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04955: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '110001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04956: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '110001110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04957: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '110001110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04958: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [16, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04959: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [16, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04960: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04961: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04962: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1100011100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04963: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1100011100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04964: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [17, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04965: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [17, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04966: Output = NZ  Instr=D5 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04967: Output = Z  Instr=D6 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '11000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04968: Output = Z  Instr=D7 ADD B1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '11000111000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04969: Output = Z  Instr=D8 RESET T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '11000111000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04970: Output = NZ  Instr=D8A INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04971: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04972: Output = Z  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04973: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04974: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04975: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04976: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04977: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04978: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04979: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04980: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04981: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04982: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04983: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04984: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04985: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04986: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04987: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04988: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04989: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04990: Output = NZ  Instr=D9 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04991: Output = Z  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04992: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04993: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [16, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04994: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [15, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04995: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [14, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04996: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [13, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04997: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [12, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04998: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [11, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
04999: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05000: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [9, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05001: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [8, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05002: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [7, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05003: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [6, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05004: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [5, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05005: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [4, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05006: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [3, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05007: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [2, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05008: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [1, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05009: Output = NZ  Instr=D10 DEC T4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05010: Output = Z  Instr=D1 TDEC R4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05011: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05012: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05013: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05014: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05015: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05016: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05017: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05018: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05019: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05020: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05021: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05022: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05023: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05024: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05025: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05026: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05027: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05028: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05029: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05030: Output = Z  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05031: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05032: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05033: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05034: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05035: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05036: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05037: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05038: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05039: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05040: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05041: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05042: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05043: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05044: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05045: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05046: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05047: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05048: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05049: Output = Z  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05050: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05051: Output = NZ  Instr=D6 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05052: Output = NZ  Instr=D7 ADD B0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, 'x100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05053: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, 'x100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05054: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [1, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05055: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [1, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05056: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05057: Output = NZ  Instr=D6 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05058: Output = NZ  Instr=D7 ADD B0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0x00011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05059: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0x00011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05060: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [2, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05061: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [2, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05062: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05063: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '11x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05064: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '01x0011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05065: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '01x0011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05066: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [3, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05067: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [3, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05068: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05069: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '110x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05070: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '011x011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05071: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '011x011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05072: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [4, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05073: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [4, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05074: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05075: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05076: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0110x11100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05077: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0110x11100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05078: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [5, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05079: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [5, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05080: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05081: Output = NZ  Instr=D6 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '11000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '0110011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05082: Output = NZ  Instr=D7 ADD B0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '01100x1100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05083: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '01100x1100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05084: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [6, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05085: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [6, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05086: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05087: Output = NZ  Instr=D6 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '110001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05088: Output = NZ  Instr=D7 ADD B0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '011000x100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05089: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '011000x100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05090: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [7, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05091: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [7, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05092: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05093: Output = NZ  Instr=D6 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05094: Output = NZ  Instr=D7 ADD B0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0110001x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05095: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0110001x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05096: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [8, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05097: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [8, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05098: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05099: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '11000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '0110001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05100: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '01100011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05101: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '01100011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05102: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [9, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05103: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [9, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05104: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05105: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '110001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05106: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '011000111x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05107: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '011000111x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05108: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [10, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05109: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [10, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05110: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05111: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05112: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0110001110x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05113: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0110001110x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05114: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [11, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05115: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [11, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05116: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05117: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '11000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05118: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '01100011100x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05119: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '01100011100x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05120: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [12, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05121: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [12, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05122: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05123: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '110001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05124: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '011000111000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05125: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '011000111000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05126: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [13, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05127: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [13, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05128: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05129: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05130: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0110001110000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05131: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0110001110000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05132: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [14, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05133: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [14, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05134: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05135: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '11000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05136: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '01100011100000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05137: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '01100011100000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05138: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [15, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05139: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [15, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05140: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05141: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '110001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05142: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '011000111000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05143: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '011000111000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05144: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [16, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05145: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [16, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05146: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05147: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05148: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0110001110000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05149: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0110001110000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05150: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [17, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05151: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [17, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05152: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05153: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '11000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05154: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '01100011100000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05155: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '01100011100000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05156: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05157: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05158: Output = Z  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05159: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05160: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05161: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05162: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05163: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05164: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05165: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05166: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05167: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05168: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05169: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05170: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05171: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05172: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05173: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05174: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05175: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05176: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05177: Output = Z  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05178: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05179: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [16, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05180: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [15, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05181: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [14, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05182: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [13, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05183: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [12, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05184: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [11, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05185: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05186: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [9, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05187: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [8, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05188: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [7, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05189: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [6, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05190: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [5, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05191: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [4, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05192: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [3, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05193: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [2, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05194: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [1, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05195: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05196: Output = Z  Instr=D1 TDEC R4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05197: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05198: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05199: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05200: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05201: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05202: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05203: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05204: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05205: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05206: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05207: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05208: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05209: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05210: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05211: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05212: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05213: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05214: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05215: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05216: Output = Z  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05217: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05218: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05219: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05220: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05221: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05222: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05223: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05224: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05225: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05226: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05227: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05228: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05229: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05230: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05231: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05232: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05233: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05234: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05235: Output = Z  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05236: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05237: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05238: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, 'x110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05239: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, 'x110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05240: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [1, '1110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05241: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [1, '1110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05242: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05243: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05244: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1x10001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05245: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1x10001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05246: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [2, '1010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05247: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [2, '1010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05248: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '1010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05249: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '1010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '11x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '1010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05250: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '10x0001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05251: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '10x0001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '1000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05252: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [3, '1000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05253: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [3, '1000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05254: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '1000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05255: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '1000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '110x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '1000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05256: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '100x001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05257: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '100x001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '1001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05258: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [4, '1001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05259: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [4, '1001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05260: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05261: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05262: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1001x01110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05263: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1001x01110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05264: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [5, '1001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05265: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [5, '1001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05266: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05267: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '11000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1001001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05268: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '10010x1110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05269: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '10010x1110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1001011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05270: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [6, '1001011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05271: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [6, '1001011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05272: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1001011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05273: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1001011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '110001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1001011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1001011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05274: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '100101x110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05275: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '100101x110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1001010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05276: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [7, '1001010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05277: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [7, '1001010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05278: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1001010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05279: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1001010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1001010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1001010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05280: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1001010x10000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05281: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1001010x10000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1001010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05282: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [8, '1001010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05283: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [8, '1001010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05284: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '1001010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05285: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '1001010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '11000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '1001010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05286: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '10010101x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05287: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '10010101x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '1001010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05288: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [9, '1001010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05289: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [9, '1001010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05290: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '1001010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05291: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '1001010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '110001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '1001010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05292: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '100101010x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05293: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '100101010x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05294: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [10, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05295: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [10, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05296: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05297: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05298: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1001010101x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05299: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1001010101x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05300: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [11, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05301: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [11, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05302: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05303: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '11000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05304: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '10010101010x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05305: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '10010101010x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05306: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [12, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05307: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [12, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05308: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05309: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '110001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05310: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '100101010100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05311: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '100101010100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05312: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [13, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05313: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [13, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05314: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05315: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05316: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1001010101000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05317: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1001010101000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05318: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [14, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05319: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [14, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05320: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05321: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '11000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05322: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '10010101010000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05323: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '10010101010000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05324: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [15, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05325: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [15, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05326: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05327: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '110001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05328: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '100101010100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05329: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '100101010100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05330: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [16, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05331: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [16, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05332: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05333: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05334: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1001010101000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05335: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1001010101000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05336: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [17, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05337: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [17, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05338: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05339: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '11000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05340: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '10010101010000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05341: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '10010101010000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05342: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05343: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05344: Output = Z  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05345: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05346: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05347: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05348: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05349: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05350: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05351: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05352: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05353: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05354: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05355: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05356: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05357: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05358: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05359: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05360: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05361: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05362: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05363: Output = Z  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05364: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05365: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [16, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05366: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [15, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05367: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [14, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05368: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [13, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05369: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [12, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05370: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [11, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05371: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05372: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [9, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05373: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [8, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05374: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [7, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05375: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [6, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05376: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [5, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05377: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [4, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05378: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [3, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05379: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [2, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05380: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [1, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05381: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05382: Output = Z  Instr=D1 TDEC R4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05383: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05384: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05385: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05386: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05387: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05388: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05389: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05390: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05391: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05392: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05393: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05394: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05395: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05396: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05397: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05398: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05399: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05400: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05401: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05402: Output = Z  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05403: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05404: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05405: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05406: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05407: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05408: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05409: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05410: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05411: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05412: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05413: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05414: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05415: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05416: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05417: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05418: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05419: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05420: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05421: Output = Z  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05422: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05423: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05424: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, 'x001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05425: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, 'x001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05426: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [1, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05427: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [1, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05428: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05429: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05430: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0x01010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05431: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0x01010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05432: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [2, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05433: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [2, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05434: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05435: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '11x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05436: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '00x1010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05437: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '00x1010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05438: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [3, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05439: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [3, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05440: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05441: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '110x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05442: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '001x010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05443: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '001x010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05444: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [4, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05445: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [4, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05446: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05447: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05448: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0011x10101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05449: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0011x10101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05450: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [5, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05451: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [5, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05452: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05453: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '11000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '0011010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05454: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '00110x0101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05455: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '00110x0101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05456: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [6, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05457: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [6, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05458: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05459: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '110001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05460: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '001100x101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05461: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '001100x101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05462: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [7, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05463: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [7, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05464: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05465: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05466: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0011000x01000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05467: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0011000x01000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05468: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [8, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05469: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [8, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05470: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05471: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '11000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '0011000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05472: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '00110001x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05473: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '00110001x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05474: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [9, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05475: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [9, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05476: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05477: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '110001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05478: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '001100011x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05479: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '001100011x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05480: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [10, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05481: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [10, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05482: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05483: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05484: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0011000111x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05485: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0011000111x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05486: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [11, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05487: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [11, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05488: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05489: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '11000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05490: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '00110001110x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05491: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '00110001110x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05492: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [12, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05493: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [12, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05494: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05495: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '110001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05496: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '001100011100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05497: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '001100011100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05498: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [13, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05499: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [13, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05500: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05501: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05502: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0011000111000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05503: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0011000111000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05504: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [14, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05505: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [14, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05506: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05507: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '11000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05508: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '00110001110000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05509: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '00110001110000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05510: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [15, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05511: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [15, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05512: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05513: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '110001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05514: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '001100011100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05515: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '001100011100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05516: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [16, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05517: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [16, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05518: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05519: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05520: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0011000111000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05521: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0011000111000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05522: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [17, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05523: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [17, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05524: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05525: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '11000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05526: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '00110001110000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05527: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '00110001110000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05528: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05529: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05530: Output = Z  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05531: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05532: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05533: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05534: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05535: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05536: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05537: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05538: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05539: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05540: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05541: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05542: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05543: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05544: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05545: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05546: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05547: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05548: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05549: Output = Z  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05550: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05551: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [16, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05552: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [15, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05553: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [14, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05554: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [13, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05555: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [12, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05556: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [11, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05557: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05558: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [9, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05559: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [8, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05560: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [7, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05561: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [6, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05562: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [5, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05563: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [4, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05564: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [3, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05565: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [2, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05566: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [1, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05567: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05568: Output = Z  Instr=D1 TDEC R4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05569: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05570: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05571: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05572: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05573: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05574: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05575: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05576: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05577: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05578: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05579: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05580: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05581: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05582: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05583: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05584: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05585: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05586: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05587: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05588: Output = Z  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05589: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05590: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05591: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05592: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05593: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05594: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05595: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05596: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05597: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05598: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05599: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05600: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05601: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05602: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05603: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05604: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05605: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05606: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05607: Output = Z  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05608: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05609: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05610: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, 'x011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05611: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, 'x011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05612: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [1, '1011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05613: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [1, '1011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05614: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05615: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1011000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05616: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1x11000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05617: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1x11000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05618: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [2, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05619: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [2, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05620: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05621: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '11x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05622: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '11x1000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05623: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '11x1000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05624: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [3, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05625: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [3, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05626: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05627: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '110x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05628: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '111x000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05629: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '111x000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05630: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [4, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05631: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [4, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05632: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05633: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05634: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1111x00111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05635: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1111x00111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05636: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [5, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05637: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [5, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05638: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05639: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '11000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1111000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05640: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '11110x0111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05641: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '11110x0111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1111010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05642: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [6, '1111010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05643: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [6, '1111010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05644: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1111010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05645: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1111010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '110001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1111010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1111010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05646: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '111101x111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05647: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '111101x111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1111011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05648: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [7, '1111011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05649: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [7, '1111011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05650: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1111011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05651: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1111011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1111011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1111011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05652: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1111011x11000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05653: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1111011x11000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1111011011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05654: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [8, '1111011011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05655: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [8, '1111011011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05656: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '1111011011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05657: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '1111011011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '11000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '1111011011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05658: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '11110110x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05659: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '11110110x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '1111011001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05660: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [9, '1111011001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05661: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [9, '1111011001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05662: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '1111011001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05663: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '1111011001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '110001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '1111011001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05664: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '111101100x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05665: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '111101100x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '1111011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05666: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [10, '1111011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05667: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [10, '1111011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05668: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1111011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05669: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1111011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1111011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05670: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1111011000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05671: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1111011000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05672: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [11, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05673: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [11, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05674: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05675: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '11000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05676: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '11110110001x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05677: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '11110110001x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05678: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [12, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05679: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [12, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05680: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05681: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '110001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05682: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '111101100010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05683: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '111101100010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05684: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [13, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05685: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [13, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05686: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05687: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05688: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1111011000100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05689: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1111011000100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05690: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [14, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05691: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [14, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05692: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05693: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '11000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05694: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '11110110001000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05695: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '11110110001000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05696: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [15, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05697: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [15, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05698: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05699: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '110001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05700: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '111101100010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05701: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '111101100010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05702: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [16, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05703: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [16, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05704: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05705: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05706: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1111011000100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05707: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1111011000100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05708: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [17, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05709: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [17, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05710: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05711: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '11000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05712: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '11110110001000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05713: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '11110110001000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05714: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05715: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05716: Output = Z  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05717: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05718: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05719: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05720: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05721: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05722: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05723: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05724: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05725: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05726: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05727: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05728: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05729: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05730: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05731: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05732: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05733: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05734: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05735: Output = Z  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05736: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05737: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [16, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05738: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [15, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05739: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [14, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05740: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [13, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05741: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [12, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05742: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [11, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05743: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05744: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [9, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05745: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [8, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05746: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [7, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05747: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [6, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05748: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [5, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05749: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [4, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05750: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [3, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05751: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [2, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05752: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [1, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05753: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05754: Output = Z  Instr=D1 TDEC R4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05755: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05756: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05757: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05758: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05759: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05760: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05761: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05762: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05763: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05764: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05765: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05766: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05767: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05768: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05769: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05770: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05771: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05772: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05773: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05774: Output = Z  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05775: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05776: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05777: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05778: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05779: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05780: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05781: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05782: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05783: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05784: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05785: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05786: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05787: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05788: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05789: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05790: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05791: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05792: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05793: Output = Z  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05794: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05795: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05796: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, 'x111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05797: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, 'x111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05798: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [1, '0111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05799: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [1, '0111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05800: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05801: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05802: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0x11011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05803: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0x11011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '0111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05804: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [2, '0111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05805: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [2, '0111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05806: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '0111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05807: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '0111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '11x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '0111011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05808: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '01x1011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05809: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '01x1011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05810: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [3, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05811: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [3, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05812: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05813: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '110x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05814: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '010x011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05815: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '010x011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '0100011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05816: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [4, '0100011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05817: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [4, '0100011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05818: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0100011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05819: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0100011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0100011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05820: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0100x11000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05821: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0100x11000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '0100111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05822: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [5, '0100111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05823: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [5, '0100111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05824: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '0100111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05825: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '0100111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '11000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '0100111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '0100111000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05826: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '01001x1000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05827: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '01001x1000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05828: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [6, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05829: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [6, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05830: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05831: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '110001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05832: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '010010x000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05833: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '010010x000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05834: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [7, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05835: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [7, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05836: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05837: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05838: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0100101x00100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
05839: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0100101x00100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05840: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [8, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05841: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [8, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05842: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05843: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '11000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '0100101000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05844: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '01001010x0100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05845: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '01001010x0100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05846: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [9, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05847: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [9, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05848: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05849: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '110001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05850: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '010010101x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05851: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '010010101x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05852: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [10, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05853: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [10, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05854: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05855: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05856: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0100101010x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05857: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0100101010x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05858: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [11, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05859: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [11, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05860: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05861: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '11000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05862: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '01001010101x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05863: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '01001010101x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05864: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [12, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05865: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [12, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05866: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05867: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '110001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05868: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '010010101010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05869: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '010010101010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05870: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [13, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05871: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [13, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05872: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05873: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05874: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0100101010100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05875: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0100101010100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05876: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [14, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05877: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [14, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05878: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05879: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '11000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05880: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '01001010101000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05881: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '01001010101000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05882: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [15, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05883: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [15, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05884: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05885: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '110001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05886: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '010010101010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05887: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '010010101010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05888: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [16, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05889: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [16, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05890: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05891: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05892: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0100101010100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05893: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0100101010100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05894: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [17, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05895: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [17, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05896: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05897: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '11000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05898: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '01001010101000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05899: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '01001010101000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05900: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05901: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05902: Output = Z  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05903: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05904: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05905: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05906: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05907: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05908: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05909: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05910: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05911: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05912: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05913: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05914: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05915: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05916: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05917: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05918: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05919: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05920: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05921: Output = Z  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05922: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05923: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [16, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05924: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [15, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05925: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [14, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05926: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [13, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05927: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [12, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05928: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [11, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05929: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05930: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [9, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05931: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [8, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05932: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [7, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05933: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [6, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05934: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [5, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05935: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [4, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05936: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [3, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05937: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [2, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05938: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [1, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05939: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05940: Output = Z  Instr=D1 TDEC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05941: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05942: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05943: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05944: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05945: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05946: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05947: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05948: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05949: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05950: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05951: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05952: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05953: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05954: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05955: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05956: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05957: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05958: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05959: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05960: Output = Z  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05961: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05962: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05963: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05964: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05965: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05966: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05967: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05968: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05969: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05970: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05971: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05972: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05973: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05974: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05975: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05976: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05977: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05978: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05979: Output = Z  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05980: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05981: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '0100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05982: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, 'x100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05983: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, 'x100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05984: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [1, '1100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05985: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [1, '1100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05986: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05987: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1100101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05988: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1x00101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
05989: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1x00101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1000101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05990: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [2, '1000101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05991: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [2, '1000101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05992: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '1000101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05993: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '1000101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '11x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '1000101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05994: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '10x0101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
05995: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '10x0101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05996: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [3, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05997: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [3, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05998: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
05999: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '110x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06000: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '101x101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06001: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '101x101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06002: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [4, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06003: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [4, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06004: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06005: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06006: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1010x01010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06007: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1010x01010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06008: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [5, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06009: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [5, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06010: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06011: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '11000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1010101010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
06012: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '10101x1010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
06013: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '10101x1010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1010111010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06014: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [6, '1010111010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06015: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [6, '1010111010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06016: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1010111010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06017: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1010111010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '110001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1010111010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1010111010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
06018: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '101011x010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
06019: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '101011x010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1010110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06020: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [7, '1010110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06021: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [7, '1010110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06022: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1010110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06023: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1010110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1010110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1010110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
06024: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1010110x10100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
06025: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1010110x10100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1010110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06026: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [8, '1010110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06027: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [8, '1010110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06028: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '1010110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06029: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '1010110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '11000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '1010110010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06030: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '10101100x0100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06031: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '10101100x0100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '1010110000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06032: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [9, '1010110000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06033: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [9, '1010110000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06034: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '1010110000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06035: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '1010110000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '110001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '1010110000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06036: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '101011000x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06037: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '101011000x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06038: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06039: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06040: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06041: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06042: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1010110001x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06043: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1010110001x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06044: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [11, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06045: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [11, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06046: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06047: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '11000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06048: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '10101100011x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06049: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '10101100011x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06050: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [12, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06051: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [12, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06052: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06053: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '110001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06054: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '101011000110x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06055: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '101011000110x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06056: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [13, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06057: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [13, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06058: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06059: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06060: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1010110001100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06061: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1010110001100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06062: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [14, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06063: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [14, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06064: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06065: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '11000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06066: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '10101100011000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06067: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '10101100011000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06068: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [15, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06069: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [15, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06070: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06071: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '110001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06072: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '101011000110000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06073: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '101011000110000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06074: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [16, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06075: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [16, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06076: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06077: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06078: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1010110001100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06079: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1010110001100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06080: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [17, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06081: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [17, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06082: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06083: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '11000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06084: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '10101100011000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06085: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '10101100011000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06086: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06087: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06088: Output = Z  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06089: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06090: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06091: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06092: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06093: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06094: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06095: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06096: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06097: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06098: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06099: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06100: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06101: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06102: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06103: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06104: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06105: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06106: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06107: Output = Z  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06108: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06109: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [16, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06110: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [15, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06111: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [14, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06112: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [13, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06113: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [12, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06114: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [11, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06115: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06116: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [9, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06117: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [8, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06118: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [7, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06119: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [6, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06120: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [5, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06121: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [4, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06122: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [3, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06123: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [2, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06124: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [1, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06125: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06126: Output = Z  Instr=D1 TDEC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06127: Output = Z  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06128: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06129: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06130: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06131: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06132: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06133: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06134: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06135: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06136: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06137: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06138: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06139: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06140: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06141: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06142: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06143: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06144: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06145: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06146: Output = Z  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06147: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06148: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06149: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06150: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06151: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06152: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06153: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06154: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06155: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06156: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06157: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06158: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06159: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06160: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06161: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06162: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06163: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06164: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06165: Output = Z  Instr=COMP NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06166: Output = Z  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06167: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06168: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06169: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 7, 'T4': [1, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06170: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06171: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [1, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06172: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 7, 'T4': [2, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06173: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06174: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [2, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06175: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 7, 'T4': [3, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06176: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06177: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [3, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06178: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 7, 'T4': [4, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06179: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06180: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [4, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06181: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 7, 'T4': [5, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06182: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06183: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [5, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06184: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 7, 'T4': [6, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06185: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06186: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [6, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06187: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 7, 'T4': [7, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06188: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06189: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [7, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06190: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 7, 'T4': [8, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06191: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06192: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [8, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06193: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 7, 'T4': [9, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06194: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06195: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [9, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06196: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06197: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06198: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06199: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 7, 'T4': [11, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06200: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06201: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [11, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06202: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 7, 'T4': [12, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06203: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06204: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [12, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06205: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 7, 'T4': [13, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06206: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06207: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [13, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06208: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 7, 'T4': [14, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06209: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06210: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [14, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06211: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 7, 'T4': [15, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06212: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06213: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [15, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06214: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 7, 'T4': [16, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06215: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06216: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [16, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06217: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 7, 'T4': [17, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06218: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06219: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06220: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06221: Output = Z  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06222: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '000010011000000000x'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06223: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '101011000110000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [18, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06224: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06225: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06226: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '00001001100000000x0'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06227: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '10101100011000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [17, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06228: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [16, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06229: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [16, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06230: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [16, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000x00'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [16, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06231: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [16, '1010110001100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [16, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06232: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [15, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06233: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [15, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06234: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [15, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '000010011000000x000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [15, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06235: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [15, '101011000110000x000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [15, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06236: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [14, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06237: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [14, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06238: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [14, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '00001001100000x0000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [14, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06239: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [14, '10101100011000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [14, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06240: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [13, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06241: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [13, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06242: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [13, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000x00000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [13, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06243: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [13, '1010110001100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [13, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06244: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [12, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06245: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [12, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06246: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [12, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '000010011000x000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [12, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06247: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [12, '101011000110x000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [12, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06248: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [11, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06249: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [11, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06250: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [11, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '00001001100x0000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [11, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06251: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [11, '10101100011x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [11, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06252: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06253: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06254: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110x00000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06255: Output = NZ  Instr=E9 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1010110001x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06256: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06257: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06258: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06259: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06260: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06261: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06262: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06263: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06264: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06265: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06266: Output = Z  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [10, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06267: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [9, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06268: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [8, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06269: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [7, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06270: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [6, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06271: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [5, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06272: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [4, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06273: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [3, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06274: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [2, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06275: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [1, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06276: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06277: Output = Z  Instr=E11 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 7, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06278: Output = NZ  Instr=EVL NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06279: Output = Z  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06280: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06281: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06282: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06283: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06284: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06285: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06286: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06287: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06288: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06289: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06290: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06291: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06292: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06293: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06294: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06295: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06296: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06297: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06298: Output = Z  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06299: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06300: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06301: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06302: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06303: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06304: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06305: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06306: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06307: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06308: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06309: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06310: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06311: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06312: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06313: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06314: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06315: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06316: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06317: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06318: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '1010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06319: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, 'x010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06320: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [1, '0010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06321: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06322: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0x10110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06323: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [2, '0010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06324: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0010110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06325: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '00x0110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0000110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06326: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [3, '0000110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06327: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0000110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06328: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '000x110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0000110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06329: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [4, '0000110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06330: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0000110001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06331: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0000x10001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06332: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [5, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06333: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0000010001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06334: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '00000x0001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0000000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06335: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [6, '0000000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06336: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0000000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06337: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '000000x001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0000000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06338: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [7, '0000000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06339: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0000000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06340: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0000000x01100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0000000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06341: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [8, '0000000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06342: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0000000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06343: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '00000000x1100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0000000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06344: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [9, '0000000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06345: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0000000001100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06346: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '000000000x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06347: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [10, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06348: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06349: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0000000000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06350: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06351: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06352: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '00000000000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06353: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06354: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06355: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '000000000000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06356: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06357: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06358: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0000000000000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06359: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06360: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06361: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '00000000000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06362: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06363: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06364: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '000000000000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06365: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06366: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06367: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0000000000000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06368: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06369: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06370: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '00000000000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06371: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06372: Output = Z  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06373: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06374: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06375: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06376: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06377: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06378: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06379: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06380: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06381: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [9, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06382: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [8, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06383: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [7, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06384: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [6, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06385: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [5, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06386: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [4, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06387: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [3, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06388: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06389: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06390: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06391: Output = Z  Instr=B5 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06392: Output = Z  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06393: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06394: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06395: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06396: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06397: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06398: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06399: Output = Z  Instr=B7 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06400: Output = NZ  Instr=B7 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06401: Output = NZ  Instr=B7 INC R3; regs={'R4': 1, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 1, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06402: Output = NZ  Instr=B7 INC R3; regs={'R4': 2, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 2, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06403: Output = NZ  Instr=B7 INC R3; regs={'R4': 3, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 3, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 4, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06404: Output = NZ  Instr=B7 INC R3; regs={'R4': 4, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 4, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 5, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06405: Output = NZ  Instr=B7 INC R3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06406: Output = Z  Instr=B8 NOP; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06407: Output = Z  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06408: Output = NZ  Instr=B9 INC R1; regs={'R4': 6, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06409: Output = NZ  Instr=B9 INC R1; regs={'R4': 6, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06410: Output = NZ  Instr=B9 INC R1; regs={'R4': 6, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06411: Output = NZ  Instr=B9 INC R1; regs={'R4': 6, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06412: Output = NZ  Instr=B9 INC R1; regs={'R4': 6, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06413: Output = NZ  Instr=B9 INC R1; regs={'R4': 6, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06414: Output = NZ  Instr=B9 INC R1; regs={'R4': 6, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06415: Output = NZ  Instr=B9 INC R1; regs={'R4': 6, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06416: Output = NZ  Instr=B9 INC R1; regs={'R4': 6, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06417: Output = NZ  Instr=B9 INC R1; regs={'R4': 6, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06418: Output = NZ  Instr=B9 INC R1; regs={'R4': 6, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06419: Output = NZ  Instr=B9 INC R1; regs={'R4': 6, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06420: Output = NZ  Instr=B9 INC R1; regs={'R4': 6, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06421: Output = NZ  Instr=B9 INC R1; regs={'R4': 6, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06422: Output = NZ  Instr=B9 INC R1; regs={'R4': 6, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06423: Output = NZ  Instr=B9 INC R1; regs={'R4': 6, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06424: Output = NZ  Instr=B9 INC R1; regs={'R4': 6, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06425: Output = NZ  Instr=B9 INC R1; regs={'R4': 6, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 6, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06426: Output = Z  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06427: Output = NZ  Instr=B10 INC R0; regs={'R4': 6, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 6, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06428: Output = NZ  Instr=B10 INC R0; regs={'R4': 6, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 6, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06429: Output = NZ  Instr=B10 INC R0; regs={'R4': 6, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 6, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06430: Output = NZ  Instr=B10 INC R0; regs={'R4': 6, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 6, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06431: Output = NZ  Instr=B10 INC R0; regs={'R4': 6, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 6, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06432: Output = NZ  Instr=B10 INC R0; regs={'R4': 6, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 6, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06433: Output = NZ  Instr=B10 INC R0; regs={'R4': 6, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 6, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06434: Output = NZ  Instr=B10 INC R0; regs={'R4': 6, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 6, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06435: Output = NZ  Instr=B10 INC R0; regs={'R4': 6, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 6, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06436: Output = NZ  Instr=B10 INC R0; regs={'R4': 6, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 6, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06437: Output = NZ  Instr=B10 INC R0; regs={'R4': 6, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 6, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06438: Output = NZ  Instr=B10 INC R0; regs={'R4': 6, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 6, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06439: Output = NZ  Instr=B10 INC R0; regs={'R4': 6, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 6, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06440: Output = NZ  Instr=B10 INC R0; regs={'R4': 6, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 6, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06441: Output = NZ  Instr=B10 INC R0; regs={'R4': 6, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 6, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06442: Output = NZ  Instr=B10 INC R0; regs={'R4': 6, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 6, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06443: Output = NZ  Instr=B10 INC R0; regs={'R4': 6, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 6, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06444: Output = NZ  Instr=B10 INC R0; regs={'R4': 6, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06445: Output = Z  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06446: Output = NZ  Instr=B12 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06447: Output = NZ  Instr=B13 READ T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06448: Output = Z  Instr=B14 RESET T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, 'x011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06449: Output = NZ  Instr=B15 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06450: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06451: Output = NZ  Instr=B12 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06452: Output = NZ  Instr=B13 READ T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06453: Output = Z  Instr=B14 RESET T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [1, '0x11101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06454: Output = NZ  Instr=B15 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06455: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06456: Output = NZ  Instr=B12 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06457: Output = Z  Instr=B13 READ T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06458: Output = NZ  Instr=B14 SET T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [2, '00x1101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06459: Output = NZ  Instr=B15 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06460: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06461: Output = NZ  Instr=B12 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06462: Output = Z  Instr=B13 READ T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06463: Output = NZ  Instr=B14 SET T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [3, '001x101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06464: Output = NZ  Instr=B15 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [3, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06465: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06466: Output = NZ  Instr=B12 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06467: Output = Z  Instr=B13 READ T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06468: Output = NZ  Instr=B14 SET T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011x01100000000000'], 'T3': [4, '0011x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06469: Output = NZ  Instr=B15 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [4, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06470: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06471: Output = NZ  Instr=B12 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06472: Output = NZ  Instr=B13 READ T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06473: Output = Z  Instr=B14 RESET T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [5, '00111x1100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06474: Output = NZ  Instr=B15 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06475: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06476: Output = NZ  Instr=B12 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06477: Output = NZ  Instr=B13 READ T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06478: Output = NZ  Instr=B14 SET T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [6, '001110x100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06479: Output = NZ  Instr=B15 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06480: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06481: Output = NZ  Instr=B12 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06482: Output = NZ  Instr=B13 READ T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06483: Output = NZ  Instr=B14 SET T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101x00000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06484: Output = NZ  Instr=B15 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06485: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06486: Output = NZ  Instr=B12 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06487: Output = Z  Instr=B13 READ T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06488: Output = Z  Instr=B14 RESET T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [8, '00111011x0000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06489: Output = NZ  Instr=B15 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06490: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06491: Output = NZ  Instr=B12 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06492: Output = Z  Instr=B13 READ T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06493: Output = Z  Instr=B14 RESET T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [9, '001110110x000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06494: Output = NZ  Instr=B15 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06495: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06496: Output = NZ  Instr=B12 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06497: Output = Z  Instr=B13 READ T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06498: Output = Z  Instr=B14 RESET T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100x00000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06499: Output = NZ  Instr=B15 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06500: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06501: Output = NZ  Instr=B12 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06502: Output = Z  Instr=B13 READ T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06503: Output = Z  Instr=B14 RESET T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [11, '00111011000x0000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06504: Output = NZ  Instr=B15 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06505: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06506: Output = NZ  Instr=B12 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06507: Output = Z  Instr=B13 READ T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06508: Output = Z  Instr=B14 RESET T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [12, '001110110000x000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06509: Output = NZ  Instr=B15 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06510: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06511: Output = NZ  Instr=B12 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06512: Output = Z  Instr=B13 READ T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06513: Output = Z  Instr=B14 RESET T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000x00000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06514: Output = NZ  Instr=B15 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06515: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06516: Output = NZ  Instr=B12 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06517: Output = Z  Instr=B13 READ T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06518: Output = Z  Instr=B14 RESET T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [14, '00111011000000x0000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06519: Output = NZ  Instr=B15 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06520: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06521: Output = NZ  Instr=B12 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06522: Output = Z  Instr=B13 READ T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06523: Output = Z  Instr=B14 RESET T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [15, '001110110000000x000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06524: Output = NZ  Instr=B15 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06525: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06526: Output = NZ  Instr=B12 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06527: Output = Z  Instr=B13 READ T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06528: Output = Z  Instr=B14 RESET T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000x00'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06529: Output = NZ  Instr=B15 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06530: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06531: Output = NZ  Instr=B12 READ T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06532: Output = Z  Instr=B13 READ T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06533: Output = Z  Instr=B14 RESET T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [17, '00111011000000000x0'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06534: Output = NZ  Instr=B15 INC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06535: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06536: Output = Z  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06537: Output = NZ  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06538: Output = NZ  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06539: Output = NZ  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06540: Output = NZ  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06541: Output = NZ  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06542: Output = NZ  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06543: Output = NZ  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06544: Output = NZ  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06545: Output = NZ  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06546: Output = NZ  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06547: Output = NZ  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06548: Output = NZ  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06549: Output = NZ  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06550: Output = NZ  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06551: Output = NZ  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06552: Output = NZ  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06553: Output = NZ  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06554: Output = NZ  Instr=B16 DEC T2; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06555: Output = Z  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06556: Output = NZ  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06557: Output = NZ  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06558: Output = NZ  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06559: Output = NZ  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06560: Output = NZ  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06561: Output = NZ  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06562: Output = NZ  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06563: Output = NZ  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06564: Output = NZ  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06565: Output = NZ  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06566: Output = NZ  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06567: Output = NZ  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06568: Output = NZ  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06569: Output = NZ  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06570: Output = NZ  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06571: Output = NZ  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06572: Output = NZ  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06573: Output = NZ  Instr=B17 DEC T3; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06574: Output = Z  Instr=ADD NOP; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06575: Output = Z  Instr=C1 TDEC R4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06576: Output = NZ  Instr=C2 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06577: Output = Z  Instr=C4 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06578: Output = Z  Instr=C1 TDEC R4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06579: Output = NZ  Instr=C2 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06580: Output = NZ  Instr=C3 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06581: Output = NZ  Instr=C2 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06582: Output = Z  Instr=C4 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06583: Output = NZ  Instr=C4 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06584: Output = Z  Instr=C1 TDEC R4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06585: Output = NZ  Instr=C2 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06586: Output = Z  Instr=C4 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06587: Output = Z  Instr=C1 TDEC R4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06588: Output = NZ  Instr=C2 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06589: Output = NZ  Instr=C3 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06590: Output = NZ  Instr=C2 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06591: Output = NZ  Instr=C3 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06592: Output = NZ  Instr=C2 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06593: Output = NZ  Instr=C3 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x1101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0001101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06594: Output = NZ  Instr=C2 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0001101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06595: Output = NZ  Instr=C3 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '000x101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06596: Output = NZ  Instr=C2 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06597: Output = NZ  Instr=C3 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000x01100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000001100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06598: Output = NZ  Instr=C2 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000001100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06599: Output = Z  Instr=C4 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '00000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06600: Output = NZ  Instr=C4 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06601: Output = NZ  Instr=C4 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06602: Output = NZ  Instr=C4 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06603: Output = NZ  Instr=C4 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06604: Output = NZ  Instr=C4 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06605: Output = Z  Instr=C1 TDEC R4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06606: Output = NZ  Instr=C2 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06607: Output = Z  Instr=C4 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06608: Output = Z  Instr=C1 TDEC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06609: Output = NZ  Instr=C2 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06610: Output = NZ  Instr=C3 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06611: Output = NZ  Instr=C2 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06612: Output = Z  Instr=C4 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06613: Output = NZ  Instr=C4 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06614: Output = Z  Instr=C1 TDEC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06615: Output = Z  Instr=C5 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06616: Output = Z  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06617: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06618: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06619: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06620: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06621: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06622: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06623: Output = Z  Instr=C7 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 6, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06624: Output = NZ  Instr=C7 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06625: Output = NZ  Instr=C7 INC R3; regs={'R4': 1, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 1, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06626: Output = NZ  Instr=C7 INC R3; regs={'R4': 2, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 2, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06627: Output = NZ  Instr=C7 INC R3; regs={'R4': 3, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 3, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 4, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06628: Output = NZ  Instr=C7 INC R3; regs={'R4': 4, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 4, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 5, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06629: Output = NZ  Instr=C7 INC R3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06630: Output = Z  Instr=MUL NOP; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06631: Output = Z  Instr=D1 TDEC R4; regs={'R4': 6, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06632: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06633: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06634: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06635: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06636: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06637: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06638: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06639: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06640: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06641: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06642: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06643: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06644: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06645: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06646: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06647: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06648: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06649: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06650: Output = NZ  Instr=D2 INC R1; regs={'R4': 5, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 5, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06651: Output = Z  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06652: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06653: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06654: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06655: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06656: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06657: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06658: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06659: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06660: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06661: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06662: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06663: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06664: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06665: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06666: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06667: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06668: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06669: Output = NZ  Instr=D3 INC R0; regs={'R4': 5, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06670: Output = Z  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06671: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06672: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06673: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, 'x000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06674: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, 'x000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06675: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06676: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06677: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06678: Output = NZ  Instr=D6 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
06679: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0x00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
06680: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0x00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06681: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [2, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06682: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [2, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06683: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06684: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '01x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06685: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '01x0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06686: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '01x0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06687: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [3, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06688: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [3, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06689: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06690: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '010x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06691: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '010x000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06692: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '010x000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06693: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [4, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06694: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [4, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06695: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06696: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06697: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0100x00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06698: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0100x00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06699: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [5, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06700: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [5, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06701: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06702: Output = NZ  Instr=D6 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '01000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
06703: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '01000x0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
06704: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '01000x0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0100010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06705: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [6, '0100010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06706: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [6, '0100010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06707: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0100010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06708: Output = NZ  Instr=D6 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0100010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '010001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0100010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0100010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
06709: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '010001x000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
06710: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '010001x000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0100011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06711: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [7, '0100011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06712: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [7, '0100011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06713: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0100011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06714: Output = NZ  Instr=D6 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0100011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0100011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0100011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
06715: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0100011x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
06716: Output = NZ  Instr=D8 SET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0100011x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06717: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [8, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06718: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [8, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06719: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06720: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '01000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06721: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '01000111x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06722: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '01000111x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06723: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [9, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06724: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [9, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06725: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06726: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '010001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06727: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '010001110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06728: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '010001110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06729: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [10, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06730: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [10, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06731: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06732: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06733: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0100011100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06734: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0100011100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06735: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [11, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06736: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [11, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06737: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06738: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '01000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06739: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '01000111000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06740: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '01000111000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06741: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [12, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06742: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [12, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06743: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06744: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '010001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06745: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '010001110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06746: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '010001110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06747: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [13, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06748: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [13, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06749: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06750: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06751: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0100011100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06752: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0100011100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06753: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [14, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06754: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [14, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06755: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06756: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '01000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06757: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '01000111000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06758: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '01000111000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06759: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [15, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06760: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [15, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06761: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06762: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '010001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06763: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '010001110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06764: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '010001110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06765: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [16, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06766: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [16, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06767: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06768: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06769: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0100011100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06770: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0100011100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06771: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [17, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06772: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [17, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06773: Output = NZ  Instr=D5 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06774: Output = Z  Instr=D6 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '01000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06775: Output = Z  Instr=D7 ADD B1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '01000111000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06776: Output = Z  Instr=D8 RESET T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '01000111000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06777: Output = NZ  Instr=D8A INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06778: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06779: Output = Z  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06780: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06781: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06782: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06783: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06784: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06785: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06786: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06787: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06788: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06789: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06790: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06791: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06792: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06793: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06794: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06795: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06796: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06797: Output = NZ  Instr=D9 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06798: Output = Z  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06799: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06800: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [16, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06801: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [15, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06802: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [14, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06803: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [13, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06804: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [12, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06805: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [11, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06806: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06807: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [9, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06808: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [8, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06809: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [7, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06810: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [6, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06811: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [5, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06812: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [4, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06813: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [3, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06814: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [2, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06815: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [1, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06816: Output = NZ  Instr=D10 DEC T4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06817: Output = Z  Instr=D1 TDEC R4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06818: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06819: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06820: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06821: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06822: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06823: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06824: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06825: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06826: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06827: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06828: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06829: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06830: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06831: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06832: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06833: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06834: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06835: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06836: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06837: Output = Z  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06838: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06839: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06840: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06841: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06842: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06843: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06844: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06845: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06846: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06847: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06848: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06849: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06850: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06851: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06852: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06853: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06854: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06855: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06856: Output = Z  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06857: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06858: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06859: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, 'x100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06860: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, 'x100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06861: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [1, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06862: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [1, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06863: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06864: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
06865: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0x00011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
06866: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0x00011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06867: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [2, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06868: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [2, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06869: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06870: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '01x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06871: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '00x0011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06872: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '00x0011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06873: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [3, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06874: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [3, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06875: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06876: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '010x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06877: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '001x011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06878: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '001x011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06879: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [4, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06880: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [4, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06881: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06882: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06883: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0010x11100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06884: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0010x11100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06885: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [5, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06886: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [5, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06887: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06888: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '01000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0010011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
06889: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '00100x1100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
06890: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '00100x1100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06891: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [6, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06892: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [6, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06893: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06894: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '010001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
06895: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '001000x100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
06896: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '001000x100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06897: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [7, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06898: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [7, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06899: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06900: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
06901: Output = NZ  Instr=D7 ADD B0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0010001x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
06902: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0010001x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06903: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [8, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06904: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [8, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06905: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06906: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '01000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0010001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06907: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '00100011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
06908: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '00100011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06909: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [9, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06910: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [9, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06911: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06912: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '010001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06913: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '001000111x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06914: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '001000111x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06915: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [10, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06916: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [10, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06917: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06918: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06919: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0010001110x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06920: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0010001110x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06921: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [11, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06922: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [11, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06923: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06924: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '01000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06925: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '00100011100x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06926: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '00100011100x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06927: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [12, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06928: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [12, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06929: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06930: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '010001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06931: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '001000111000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06932: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '001000111000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06933: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [13, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06934: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [13, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06935: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06936: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06937: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0010001110000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06938: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0010001110000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06939: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [14, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06940: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [14, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06941: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06942: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '01000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06943: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '00100011100000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06944: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '00100011100000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06945: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [15, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06946: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [15, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06947: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06948: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '010001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06949: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '001000111000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06950: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '001000111000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06951: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [16, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06952: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [16, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06953: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06954: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06955: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0010001110000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06956: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0010001110000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06957: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [17, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06958: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [17, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06959: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06960: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '01000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06961: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '00100011100000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06962: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '00100011100000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06963: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06964: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06965: Output = Z  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06966: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06967: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06968: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06969: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06970: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06971: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06972: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06973: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06974: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06975: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06976: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06977: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06978: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06979: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06980: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06981: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06982: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06983: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06984: Output = Z  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06985: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06986: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [16, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06987: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [15, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06988: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [14, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06989: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [13, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06990: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [12, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06991: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [11, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06992: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06993: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [9, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06994: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [8, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06995: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [7, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06996: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [6, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06997: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [5, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06998: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [4, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
06999: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [3, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07000: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [2, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07001: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [1, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07002: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07003: Output = Z  Instr=D1 TDEC R4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07004: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07005: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07006: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07007: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07008: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07009: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07010: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07011: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07012: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07013: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07014: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07015: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07016: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07017: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07018: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07019: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07020: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07021: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07022: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07023: Output = Z  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07024: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07025: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07026: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07027: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07028: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07029: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07030: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07031: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07032: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07033: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07034: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07035: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07036: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07037: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07038: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07039: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07040: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07041: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07042: Output = Z  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07043: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07044: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07045: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, 'x010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07046: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, 'x010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07047: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [1, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07048: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [1, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07049: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07050: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0010001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07051: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0x10001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07052: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0x10001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07053: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [2, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07054: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [2, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07055: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07056: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '01x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07057: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '01x0001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07058: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '01x0001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07059: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [3, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07060: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [3, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07061: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07062: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '010x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07063: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '011x001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07064: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '011x001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07065: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [4, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07066: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [4, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07067: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07068: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07069: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0110x01110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07070: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0110x01110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07071: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [5, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07072: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [5, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07073: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07074: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '01000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0110001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07075: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '01100x1110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07076: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '01100x1110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0110011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07077: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [6, '0110011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07078: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [6, '0110011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07079: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0110011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07080: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0110011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '010001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0110011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0110011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07081: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '011001x110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07082: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '011001x110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0110010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07083: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [7, '0110010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07084: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [7, '0110010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07085: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0110010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07086: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0110010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0110010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0110010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
07087: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0110010x10000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
07088: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0110010x10000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0110010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07089: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [8, '0110010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07090: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [8, '0110010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07091: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0110010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07092: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0110010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '01000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0110010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07093: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '01100101x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07094: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '01100101x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0110010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07095: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [9, '0110010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07096: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [9, '0110010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07097: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0110010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07098: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0110010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '010001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0110010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07099: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '011001010x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07100: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '011001010x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07101: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [10, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07102: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [10, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07103: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07104: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07105: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0110010101x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07106: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0110010101x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07107: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [11, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07108: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [11, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07109: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07110: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '01000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07111: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '01100101010x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07112: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '01100101010x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07113: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [12, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07114: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [12, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07115: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07116: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '010001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07117: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '011001010100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07118: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '011001010100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07119: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [13, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07120: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [13, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07121: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07122: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07123: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0110010101000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07124: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0110010101000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07125: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [14, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07126: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [14, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07127: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07128: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '01000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07129: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '01100101010000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07130: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '01100101010000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07131: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [15, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07132: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [15, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07133: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07134: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '010001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07135: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '011001010100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07136: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '011001010100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07137: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [16, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07138: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [16, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07139: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07140: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07141: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0110010101000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07142: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0110010101000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07143: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [17, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07144: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [17, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07145: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07146: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '01000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07147: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '01100101010000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07148: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '01100101010000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07149: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07150: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07151: Output = Z  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07152: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07153: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07154: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07155: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07156: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07157: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07158: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07159: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07160: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07161: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07162: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07163: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07164: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07165: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07166: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07167: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07168: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07169: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07170: Output = Z  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07171: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07172: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [16, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07173: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [15, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07174: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [14, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07175: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [13, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07176: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [12, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07177: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [11, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07178: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07179: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [9, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07180: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [8, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07181: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [7, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07182: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [6, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07183: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [5, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07184: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [4, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07185: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [3, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07186: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [2, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07187: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [1, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07188: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07189: Output = Z  Instr=D1 TDEC R4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07190: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07191: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07192: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07193: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07194: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07195: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07196: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07197: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07198: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07199: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07200: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07201: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07202: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07203: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07204: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07205: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07206: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07207: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07208: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07209: Output = Z  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07210: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07211: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07212: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07213: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07214: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07215: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07216: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07217: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07218: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07219: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07220: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07221: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07222: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07223: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07224: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07225: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07226: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07227: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07228: Output = Z  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07229: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07230: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07231: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, 'x110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07232: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, 'x110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07233: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [1, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07234: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [1, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07235: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07236: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0110010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07237: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0x10010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07238: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0x10010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07239: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [2, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07240: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [2, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07241: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07242: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '01x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07243: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '00x0010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07244: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '00x0010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07245: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [3, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07246: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [3, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07247: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07248: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '010x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07249: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '000x010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07250: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '000x010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07251: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [4, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07252: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [4, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07253: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07254: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07255: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0001x10101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07256: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0001x10101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07257: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [5, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07258: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [5, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07259: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07260: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '01000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0001010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07261: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '00010x0101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07262: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '00010x0101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07263: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [6, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07264: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [6, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07265: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07266: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '010001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
07267: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '000100x101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
07268: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '000100x101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07269: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [7, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07270: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [7, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07271: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07272: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
07273: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0001000x01000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
07274: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0001000x01000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07275: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [8, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07276: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [8, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07277: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07278: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '01000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0001000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07279: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '00010001x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07280: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '00010001x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07281: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [9, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07282: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [9, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07283: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07284: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '010001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07285: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '000100011x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07286: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '000100011x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07287: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [10, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07288: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [10, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07289: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07290: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07291: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0001000111x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07292: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0001000111x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07293: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [11, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07294: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [11, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07295: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07296: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '01000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07297: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '00010001110x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07298: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '00010001110x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07299: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [12, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07300: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [12, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07301: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07302: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '010001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07303: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '000100011100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07304: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '000100011100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07305: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [13, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07306: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [13, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07307: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07308: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07309: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0001000111000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07310: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0001000111000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07311: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [14, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07312: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [14, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07313: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07314: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '01000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07315: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '00010001110000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07316: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '00010001110000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07317: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [15, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07318: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [15, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07319: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07320: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '010001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07321: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '000100011100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07322: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '000100011100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07323: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [16, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07324: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [16, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07325: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07326: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07327: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0001000111000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07328: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0001000111000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07329: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [17, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07330: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [17, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07331: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07332: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '01000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07333: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '00010001110000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07334: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '00010001110000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07335: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07336: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07337: Output = Z  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07338: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07339: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07340: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07341: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07342: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07343: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07344: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07345: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07346: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07347: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07348: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07349: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07350: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07351: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07352: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07353: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07354: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07355: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07356: Output = Z  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07357: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07358: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [16, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07359: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [15, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07360: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [14, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07361: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [13, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07362: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [12, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07363: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [11, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07364: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07365: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [9, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07366: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [8, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07367: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [7, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07368: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [6, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07369: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [5, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07370: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [4, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07371: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [3, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07372: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [2, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07373: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [1, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07374: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07375: Output = Z  Instr=D1 TDEC R4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07376: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07377: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07378: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07379: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07380: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07381: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07382: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07383: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07384: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07385: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07386: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07387: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07388: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07389: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07390: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07391: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07392: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07393: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07394: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07395: Output = Z  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07396: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07397: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07398: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07399: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07400: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07401: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07402: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07403: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07404: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07405: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07406: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07407: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07408: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07409: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07410: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07411: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07412: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07413: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07414: Output = Z  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07415: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07416: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07417: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, 'x001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07418: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, 'x001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07419: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [1, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07420: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [1, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07421: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07422: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0001000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07423: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0x01000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07424: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0x01000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07425: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [2, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07426: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [2, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07427: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07428: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '01x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07429: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '01x1000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07430: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '01x1000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07431: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [3, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07432: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [3, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07433: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07434: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '010x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07435: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '010x000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07436: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '010x000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07437: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [4, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07438: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [4, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07439: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07440: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07441: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0101x00111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07442: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0101x00111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07443: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [5, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07444: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [5, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07445: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07446: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '01000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0101000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07447: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '01010x0111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07448: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '01010x0111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0101010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07449: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [6, '0101010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07450: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [6, '0101010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07451: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0101010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07452: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0101010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '010001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0101010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0101010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07453: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '010101x111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07454: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '010101x111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0101011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07455: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [7, '0101011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07456: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [7, '0101011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07457: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0101011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07458: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0101011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0101011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0101011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07459: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0101011x11000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07460: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0101011x11000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0101011011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07461: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [8, '0101011011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07462: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [8, '0101011011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07463: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0101011011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07464: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0101011011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '01000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0101011011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07465: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '01010110x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07466: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '01010110x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0101011001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07467: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [9, '0101011001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07468: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [9, '0101011001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07469: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0101011001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07470: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0101011001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '010001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0101011001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07471: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '010101100x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07472: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '010101100x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0101011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07473: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [10, '0101011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07474: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [10, '0101011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07475: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0101011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07476: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0101011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0101011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07477: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0101011000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07478: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0101011000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07479: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [11, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07480: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [11, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07481: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07482: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '01000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07483: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '01010110001x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07484: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '01010110001x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07485: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [12, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07486: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [12, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07487: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07488: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '010001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07489: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '010101100010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07490: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '010101100010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07491: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [13, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07492: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [13, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07493: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07494: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07495: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0101011000100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07496: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0101011000100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07497: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [14, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07498: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [14, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07499: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07500: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '01000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07501: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '01010110001000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07502: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '01010110001000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07503: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [15, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07504: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [15, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07505: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07506: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '010001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07507: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '010101100010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07508: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '010101100010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07509: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [16, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07510: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [16, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07511: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07512: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07513: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0101011000100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07514: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0101011000100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07515: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [17, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07516: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [17, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07517: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07518: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '01000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07519: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '01010110001000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07520: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '01010110001000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07521: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07522: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07523: Output = Z  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07524: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07525: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07526: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07527: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07528: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07529: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07530: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07531: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07532: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07533: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07534: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07535: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07536: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07537: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07538: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07539: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07540: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07541: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07542: Output = Z  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07543: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07544: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [16, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07545: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [15, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07546: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [14, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07547: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [13, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07548: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [12, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07549: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [11, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07550: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07551: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [9, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07552: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [8, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07553: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [7, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07554: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [6, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07555: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [5, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07556: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [4, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07557: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [3, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07558: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [2, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07559: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [1, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07560: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07561: Output = Z  Instr=D1 TDEC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07562: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07563: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07564: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07565: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07566: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07567: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07568: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07569: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07570: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07571: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07572: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07573: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07574: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07575: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07576: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07577: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07578: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07579: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07580: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07581: Output = Z  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07582: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07583: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07584: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07585: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07586: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07587: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07588: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07589: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07590: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07591: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07592: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07593: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07594: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07595: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07596: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07597: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07598: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07599: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07600: Output = Z  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07601: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07602: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07603: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, 'x101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07604: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, 'x101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07605: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [1, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07606: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [1, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07607: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07608: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0101011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07609: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0x01011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07610: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0x01011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0001011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07611: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [2, '0001011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07612: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [2, '0001011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07613: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0001011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07614: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0001011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '01x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0001011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07615: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '00x1011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07616: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '00x1011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07617: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [3, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07618: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [3, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07619: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07620: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '010x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07621: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '001x011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07622: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '001x011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07623: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [4, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07624: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [4, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07625: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07626: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07627: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0011x11000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07628: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0011x11000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07629: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [5, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07630: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [5, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07631: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07632: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '01000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0011011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07633: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '00110x1000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
07634: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '00110x1000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07635: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [6, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07636: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [6, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07637: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07638: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '010001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
07639: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '001100x000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
07640: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '001100x000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07641: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [7, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07642: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [7, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07643: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07644: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
07645: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0011001x00100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
07646: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0011001x00100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07647: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [8, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07648: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [8, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07649: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07650: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '01000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0011001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07651: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '00110010x0100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
07652: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '00110010x0100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07653: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [9, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07654: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [9, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07655: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07656: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '010001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07657: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '001100101x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07658: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '001100101x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07659: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07660: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07661: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07662: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07663: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0011001010x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07664: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0011001010x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07665: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [11, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07666: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [11, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07667: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07668: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '01000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07669: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '00110010101x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07670: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '00110010101x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07671: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [12, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07672: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [12, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07673: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07674: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '010001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07675: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '001100101010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07676: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '001100101010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07677: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [13, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07678: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [13, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07679: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07680: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07681: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0011001010100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07682: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0011001010100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07683: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [14, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07684: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [14, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07685: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07686: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '01000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07687: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '00110010101000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07688: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '00110010101000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07689: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [15, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07690: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [15, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07691: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07692: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '010001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07693: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '001100101010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07694: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '001100101010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07695: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [16, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07696: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [16, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07697: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07698: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07699: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0011001010100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07700: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0011001010100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07701: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [17, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07702: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [17, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07703: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07704: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '01000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07705: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '00110010101000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07706: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '00110010101000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07707: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07708: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07709: Output = Z  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07710: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07711: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07712: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07713: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07714: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07715: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07716: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07717: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07718: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07719: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07720: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07721: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07722: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07723: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07724: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07725: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07726: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07727: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07728: Output = Z  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07729: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07730: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [16, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07731: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [15, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07732: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [14, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07733: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [13, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07734: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [12, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07735: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [11, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07736: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07737: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [9, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07738: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [8, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07739: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [7, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07740: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [6, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07741: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [5, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07742: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [4, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07743: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [3, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07744: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [2, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07745: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [1, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07746: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07747: Output = Z  Instr=D1 TDEC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07748: Output = Z  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07749: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07750: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07751: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07752: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07753: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07754: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07755: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07756: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07757: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07758: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07759: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07760: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07761: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07762: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07763: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07764: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07765: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07766: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07767: Output = Z  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07768: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07769: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07770: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07771: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07772: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07773: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07774: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07775: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07776: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07777: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07778: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07779: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07780: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07781: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07782: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07783: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07784: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07785: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07786: Output = Z  Instr=COMP NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07787: Output = Z  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07788: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07789: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07790: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 6, 'T4': [1, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07791: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07792: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [1, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07793: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 6, 'T4': [2, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07794: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07795: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [2, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07796: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 6, 'T4': [3, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07797: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07798: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [3, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07799: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 6, 'T4': [4, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07800: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07801: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [4, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07802: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 6, 'T4': [5, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07803: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07804: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [5, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07805: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 6, 'T4': [6, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07806: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07807: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [6, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07808: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 6, 'T4': [7, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07809: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07810: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [7, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07811: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 6, 'T4': [8, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07812: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07813: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [8, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07814: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 6, 'T4': [9, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07815: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07816: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [9, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07817: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07818: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07819: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07820: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 6, 'T4': [11, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07821: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07822: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [11, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07823: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 6, 'T4': [12, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07824: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07825: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [12, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07826: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 6, 'T4': [13, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07827: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07828: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [13, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07829: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 6, 'T4': [14, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07830: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07831: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [14, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07832: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 6, 'T4': [15, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07833: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07834: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [15, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07835: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 6, 'T4': [16, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07836: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07837: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [16, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07838: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 6, 'T4': [17, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07839: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07840: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07841: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07842: Output = Z  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07843: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '000010011000000000x'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07844: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '001100101010000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [18, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07845: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07846: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07847: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '00001001100000000x0'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07848: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '00110010101000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [17, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07849: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [16, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07850: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [16, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07851: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [16, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000x00'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [16, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07852: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [16, '0011001010100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [16, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07853: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [15, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07854: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [15, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07855: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [15, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '000010011000000x000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [15, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07856: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [15, '001100101010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [15, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07857: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [14, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07858: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [14, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07859: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [14, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '00001001100000x0000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [14, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07860: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [14, '00110010101000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [14, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07861: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [13, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07862: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [13, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07863: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [13, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000x00000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [13, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07864: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [13, '0011001010100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [13, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07865: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [12, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07866: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [12, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07867: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [12, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '000010011000x000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [12, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07868: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [12, '001100101010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [12, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07869: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [11, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07870: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [11, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07871: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [11, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '00001001100x0000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [11, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07872: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [11, '00110010101x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [11, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07873: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07874: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07875: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110x00000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07876: Output = NZ  Instr=E9 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0011001010x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07877: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07878: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07879: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07880: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07881: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07882: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07883: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07884: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07885: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07886: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07887: Output = Z  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [10, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07888: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [9, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07889: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [8, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07890: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [7, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07891: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [6, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07892: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [5, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07893: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [4, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07894: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [3, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07895: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [2, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07896: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [1, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07897: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07898: Output = Z  Instr=E11 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 6, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07899: Output = NZ  Instr=EVL NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07900: Output = Z  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07901: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07902: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07903: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07904: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07905: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07906: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07907: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07908: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07909: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07910: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07911: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07912: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07913: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07914: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07915: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07916: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07917: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07918: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07919: Output = Z  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07920: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07921: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07922: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07923: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07924: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07925: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07926: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07927: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07928: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07929: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07930: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07931: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07932: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07933: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07934: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07935: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07936: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07937: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07938: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07939: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07940: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, 'x011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07941: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [1, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07942: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07943: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '0x11001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07944: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [2, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07945: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '0011001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07946: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '00x1001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '0001001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07947: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [3, '0001001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07948: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '0001001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07949: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '000x001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '0000001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07950: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [4, '0000001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07951: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '0000001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07952: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '0000x01010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '0000001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07953: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [5, '0000001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07954: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '0000001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07955: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '00000x1010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '0000001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07956: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [6, '0000001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07957: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '0000001010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07958: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '000000x010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '0000000010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07959: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [7, '0000000010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07960: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '0000000010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07961: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '0000000x10100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '0000000010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07962: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [8, '0000000010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07963: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '0000000010100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07964: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '00000000x0100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07965: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [9, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07966: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07967: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '000000000x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07968: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [10, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07969: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07970: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '0000000000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07971: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07972: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07973: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '00000000000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07974: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07975: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07976: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '000000000000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07977: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07978: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07979: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '0000000000000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07980: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07981: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07982: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '00000000000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07983: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07984: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07985: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '000000000000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07986: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07987: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07988: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '0000000000000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07989: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07990: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07991: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '00000000000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07992: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07993: Output = Z  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07994: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07995: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07996: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07997: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07998: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
07999: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08000: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08001: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08002: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [9, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08003: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [8, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08004: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [7, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08005: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [6, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08006: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [5, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08007: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [4, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08008: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [3, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08009: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08010: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08011: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08012: Output = Z  Instr=B5 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08013: Output = Z  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08014: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08015: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08016: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08017: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08018: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08019: Output = Z  Instr=B7 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08020: Output = NZ  Instr=B7 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08021: Output = NZ  Instr=B7 INC R3; regs={'R4': 1, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 1, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08022: Output = NZ  Instr=B7 INC R3; regs={'R4': 2, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 2, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08023: Output = NZ  Instr=B7 INC R3; regs={'R4': 3, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 3, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 4, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08024: Output = NZ  Instr=B7 INC R3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08025: Output = Z  Instr=B8 NOP; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08026: Output = Z  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08027: Output = NZ  Instr=B9 INC R1; regs={'R4': 5, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08028: Output = NZ  Instr=B9 INC R1; regs={'R4': 5, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08029: Output = NZ  Instr=B9 INC R1; regs={'R4': 5, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08030: Output = NZ  Instr=B9 INC R1; regs={'R4': 5, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08031: Output = NZ  Instr=B9 INC R1; regs={'R4': 5, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08032: Output = NZ  Instr=B9 INC R1; regs={'R4': 5, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08033: Output = NZ  Instr=B9 INC R1; regs={'R4': 5, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08034: Output = NZ  Instr=B9 INC R1; regs={'R4': 5, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08035: Output = NZ  Instr=B9 INC R1; regs={'R4': 5, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08036: Output = NZ  Instr=B9 INC R1; regs={'R4': 5, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08037: Output = NZ  Instr=B9 INC R1; regs={'R4': 5, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08038: Output = NZ  Instr=B9 INC R1; regs={'R4': 5, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08039: Output = NZ  Instr=B9 INC R1; regs={'R4': 5, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08040: Output = NZ  Instr=B9 INC R1; regs={'R4': 5, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08041: Output = NZ  Instr=B9 INC R1; regs={'R4': 5, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08042: Output = NZ  Instr=B9 INC R1; regs={'R4': 5, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08043: Output = NZ  Instr=B9 INC R1; regs={'R4': 5, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08044: Output = NZ  Instr=B9 INC R1; regs={'R4': 5, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 5, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08045: Output = Z  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08046: Output = NZ  Instr=B10 INC R0; regs={'R4': 5, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 5, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08047: Output = NZ  Instr=B10 INC R0; regs={'R4': 5, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 5, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08048: Output = NZ  Instr=B10 INC R0; regs={'R4': 5, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 5, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08049: Output = NZ  Instr=B10 INC R0; regs={'R4': 5, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 5, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08050: Output = NZ  Instr=B10 INC R0; regs={'R4': 5, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 5, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08051: Output = NZ  Instr=B10 INC R0; regs={'R4': 5, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 5, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08052: Output = NZ  Instr=B10 INC R0; regs={'R4': 5, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 5, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08053: Output = NZ  Instr=B10 INC R0; regs={'R4': 5, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 5, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08054: Output = NZ  Instr=B10 INC R0; regs={'R4': 5, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 5, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08055: Output = NZ  Instr=B10 INC R0; regs={'R4': 5, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 5, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08056: Output = NZ  Instr=B10 INC R0; regs={'R4': 5, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 5, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08057: Output = NZ  Instr=B10 INC R0; regs={'R4': 5, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 5, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08058: Output = NZ  Instr=B10 INC R0; regs={'R4': 5, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 5, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08059: Output = NZ  Instr=B10 INC R0; regs={'R4': 5, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 5, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08060: Output = NZ  Instr=B10 INC R0; regs={'R4': 5, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 5, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08061: Output = NZ  Instr=B10 INC R0; regs={'R4': 5, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 5, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08062: Output = NZ  Instr=B10 INC R0; regs={'R4': 5, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 5, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08063: Output = NZ  Instr=B10 INC R0; regs={'R4': 5, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08064: Output = Z  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08065: Output = NZ  Instr=B12 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08066: Output = Z  Instr=B13 READ T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08067: Output = Z  Instr=B14 RESET T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, 'x011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08068: Output = NZ  Instr=B15 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [0, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08069: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08070: Output = NZ  Instr=B12 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0100011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08071: Output = NZ  Instr=B13 READ T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08072: Output = Z  Instr=B14 RESET T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [1, '0x11101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08073: Output = NZ  Instr=B15 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08074: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08075: Output = NZ  Instr=B12 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08076: Output = Z  Instr=B13 READ T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08077: Output = NZ  Instr=B14 SET T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [2, '00x1101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08078: Output = NZ  Instr=B15 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08079: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08080: Output = NZ  Instr=B12 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08081: Output = Z  Instr=B13 READ T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08082: Output = NZ  Instr=B14 SET T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [3, '001x101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08083: Output = NZ  Instr=B15 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [3, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08084: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08085: Output = NZ  Instr=B12 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08086: Output = Z  Instr=B13 READ T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08087: Output = NZ  Instr=B14 SET T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011x01100000000000'], 'T3': [4, '0011x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08088: Output = NZ  Instr=B15 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [4, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08089: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08090: Output = NZ  Instr=B12 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08091: Output = NZ  Instr=B13 READ T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08092: Output = Z  Instr=B14 RESET T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [5, '00111x1100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08093: Output = NZ  Instr=B15 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08094: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08095: Output = NZ  Instr=B12 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08096: Output = NZ  Instr=B13 READ T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08097: Output = NZ  Instr=B14 SET T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [6, '001110x100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08098: Output = NZ  Instr=B15 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08099: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08100: Output = NZ  Instr=B12 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08101: Output = NZ  Instr=B13 READ T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08102: Output = NZ  Instr=B14 SET T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101x00000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08103: Output = NZ  Instr=B15 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08104: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08105: Output = NZ  Instr=B12 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08106: Output = Z  Instr=B13 READ T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08107: Output = Z  Instr=B14 RESET T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [8, '00111011x0000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08108: Output = NZ  Instr=B15 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08109: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08110: Output = NZ  Instr=B12 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08111: Output = Z  Instr=B13 READ T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08112: Output = Z  Instr=B14 RESET T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [9, '001110110x000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08113: Output = NZ  Instr=B15 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08114: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08115: Output = NZ  Instr=B12 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08116: Output = Z  Instr=B13 READ T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08117: Output = Z  Instr=B14 RESET T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100x00000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08118: Output = NZ  Instr=B15 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08119: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08120: Output = NZ  Instr=B12 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08121: Output = Z  Instr=B13 READ T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08122: Output = Z  Instr=B14 RESET T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [11, '00111011000x0000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08123: Output = NZ  Instr=B15 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08124: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08125: Output = NZ  Instr=B12 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08126: Output = Z  Instr=B13 READ T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08127: Output = Z  Instr=B14 RESET T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [12, '001110110000x000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08128: Output = NZ  Instr=B15 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08129: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08130: Output = NZ  Instr=B12 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08131: Output = Z  Instr=B13 READ T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08132: Output = Z  Instr=B14 RESET T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000x00000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08133: Output = NZ  Instr=B15 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08134: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08135: Output = NZ  Instr=B12 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08136: Output = Z  Instr=B13 READ T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08137: Output = Z  Instr=B14 RESET T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [14, '00111011000000x0000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08138: Output = NZ  Instr=B15 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08139: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08140: Output = NZ  Instr=B12 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08141: Output = Z  Instr=B13 READ T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08142: Output = Z  Instr=B14 RESET T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [15, '001110110000000x000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08143: Output = NZ  Instr=B15 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08144: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08145: Output = NZ  Instr=B12 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08146: Output = Z  Instr=B13 READ T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08147: Output = Z  Instr=B14 RESET T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000x00'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08148: Output = NZ  Instr=B15 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08149: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08150: Output = NZ  Instr=B12 READ T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08151: Output = Z  Instr=B13 READ T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08152: Output = Z  Instr=B14 RESET T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [17, '00111011000000000x0'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08153: Output = NZ  Instr=B15 INC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08154: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08155: Output = Z  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08156: Output = NZ  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08157: Output = NZ  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08158: Output = NZ  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08159: Output = NZ  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08160: Output = NZ  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08161: Output = NZ  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08162: Output = NZ  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08163: Output = NZ  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08164: Output = NZ  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08165: Output = NZ  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08166: Output = NZ  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08167: Output = NZ  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08168: Output = NZ  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08169: Output = NZ  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08170: Output = NZ  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08171: Output = NZ  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08172: Output = NZ  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08173: Output = NZ  Instr=B16 DEC T2; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08174: Output = Z  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08175: Output = NZ  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08176: Output = NZ  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08177: Output = NZ  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08178: Output = NZ  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08179: Output = NZ  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08180: Output = NZ  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08181: Output = NZ  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08182: Output = NZ  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08183: Output = NZ  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08184: Output = NZ  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08185: Output = NZ  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08186: Output = NZ  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08187: Output = NZ  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08188: Output = NZ  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08189: Output = NZ  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08190: Output = NZ  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08191: Output = NZ  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08192: Output = NZ  Instr=B17 DEC T3; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08193: Output = Z  Instr=ADD NOP; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08194: Output = Z  Instr=C1 TDEC R4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08195: Output = NZ  Instr=C2 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08196: Output = Z  Instr=C4 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08197: Output = Z  Instr=C1 TDEC R4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08198: Output = NZ  Instr=C2 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08199: Output = NZ  Instr=C3 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08200: Output = NZ  Instr=C2 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08201: Output = Z  Instr=C4 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08202: Output = NZ  Instr=C4 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08203: Output = Z  Instr=C1 TDEC R4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08204: Output = NZ  Instr=C2 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08205: Output = Z  Instr=C4 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08206: Output = Z  Instr=C1 TDEC R4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08207: Output = NZ  Instr=C2 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08208: Output = NZ  Instr=C3 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08209: Output = NZ  Instr=C2 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08210: Output = NZ  Instr=C3 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08211: Output = NZ  Instr=C2 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08212: Output = NZ  Instr=C3 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x1101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0001101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08213: Output = NZ  Instr=C2 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0001101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08214: Output = NZ  Instr=C3 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '000x101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08215: Output = NZ  Instr=C2 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08216: Output = NZ  Instr=C3 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000x01100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000001100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08217: Output = NZ  Instr=C2 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000001100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08218: Output = Z  Instr=C4 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '00000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08219: Output = NZ  Instr=C4 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08220: Output = NZ  Instr=C4 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08221: Output = NZ  Instr=C4 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08222: Output = NZ  Instr=C4 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08223: Output = NZ  Instr=C4 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08224: Output = Z  Instr=C1 TDEC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08225: Output = NZ  Instr=C2 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08226: Output = Z  Instr=C4 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08227: Output = Z  Instr=C1 TDEC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08228: Output = Z  Instr=C5 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08229: Output = Z  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08230: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08231: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08232: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08233: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08234: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08235: Output = Z  Instr=C7 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 5, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08236: Output = NZ  Instr=C7 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08237: Output = NZ  Instr=C7 INC R3; regs={'R4': 1, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 1, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08238: Output = NZ  Instr=C7 INC R3; regs={'R4': 2, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 2, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08239: Output = NZ  Instr=C7 INC R3; regs={'R4': 3, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 3, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 4, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08240: Output = NZ  Instr=C7 INC R3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08241: Output = Z  Instr=MUL NOP; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08242: Output = Z  Instr=D1 TDEC R4; regs={'R4': 5, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08243: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08244: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08245: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08246: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08247: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08248: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08249: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08250: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08251: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08252: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08253: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08254: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08255: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08256: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08257: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08258: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08259: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08260: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08261: Output = NZ  Instr=D2 INC R1; regs={'R4': 4, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 4, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08262: Output = Z  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08263: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08264: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08265: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08266: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08267: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08268: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08269: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08270: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08271: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08272: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08273: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08274: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08275: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08276: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08277: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08278: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08279: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08280: Output = NZ  Instr=D3 INC R0; regs={'R4': 4, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08281: Output = Z  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08282: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08283: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08284: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, 'x000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08285: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, 'x000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08286: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08287: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08288: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08289: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08290: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1x00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08291: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1x00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08292: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [2, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08293: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [2, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08294: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08295: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '10x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08296: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '10x0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08297: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '10x0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08298: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [3, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08299: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [3, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08300: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08301: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '100x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08302: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '100x000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08303: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '100x000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08304: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [4, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08305: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [4, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08306: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08307: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08308: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1000x00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08309: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1000x00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08310: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [5, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08311: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [5, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08312: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08313: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '10000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08314: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '10000x0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08315: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '10000x0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '1000010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08316: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [6, '1000010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08317: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [6, '1000010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08318: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '1000010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08319: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '1000010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '100001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '1000010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '1000010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08320: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '100001x000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08321: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '100001x000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '1000011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08322: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [7, '1000011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08323: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [7, '1000011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08324: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1000011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08325: Output = NZ  Instr=D6 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1000011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1000011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1000011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08326: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1000011x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08327: Output = NZ  Instr=D8 SET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1000011x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08328: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [8, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08329: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [8, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08330: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08331: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '10000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08332: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '10000111x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08333: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '10000111x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08334: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [9, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08335: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [9, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08336: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08337: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '100001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08338: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '100001110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08339: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '100001110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08340: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [10, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08341: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [10, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08342: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08343: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08344: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1000011100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08345: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1000011100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08346: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [11, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08347: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [11, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08348: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08349: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '10000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08350: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '10000111000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08351: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '10000111000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08352: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [12, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08353: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [12, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08354: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08355: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '100001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08356: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '100001110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08357: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '100001110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08358: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [13, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08359: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [13, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08360: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08361: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08362: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1000011100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08363: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1000011100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08364: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [14, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08365: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [14, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08366: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08367: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '10000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08368: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '10000111000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08369: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '10000111000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08370: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [15, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08371: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [15, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08372: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08373: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '100001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08374: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '100001110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08375: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '100001110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08376: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [16, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08377: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [16, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08378: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08379: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08380: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1000011100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08381: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1000011100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08382: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [17, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08383: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [17, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08384: Output = NZ  Instr=D5 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08385: Output = Z  Instr=D6 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '10000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08386: Output = Z  Instr=D7 ADD B1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '10000111000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08387: Output = Z  Instr=D8 RESET T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '10000111000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08388: Output = NZ  Instr=D8A INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08389: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08390: Output = Z  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08391: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08392: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08393: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08394: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08395: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08396: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08397: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08398: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08399: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08400: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08401: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08402: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08403: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08404: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08405: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08406: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08407: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08408: Output = NZ  Instr=D9 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08409: Output = Z  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08410: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08411: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [16, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08412: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [15, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08413: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [14, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08414: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [13, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08415: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [12, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08416: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [11, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08417: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08418: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [9, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08419: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [8, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08420: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [7, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08421: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [6, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08422: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [5, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08423: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [4, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08424: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [3, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08425: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [2, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08426: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [1, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08427: Output = NZ  Instr=D10 DEC T4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08428: Output = Z  Instr=D1 TDEC R4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08429: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08430: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08431: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08432: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08433: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08434: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08435: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08436: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08437: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08438: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08439: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08440: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08441: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08442: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08443: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08444: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08445: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08446: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08447: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08448: Output = Z  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08449: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08450: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08451: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08452: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08453: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08454: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08455: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08456: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08457: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08458: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08459: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08460: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08461: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08462: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08463: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08464: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08465: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08466: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08467: Output = Z  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08468: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08469: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08470: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, 'x000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08471: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, 'x000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08472: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [1, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08473: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [1, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08474: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08475: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08476: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '0x00011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08477: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '0x00011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08478: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [2, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08479: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [2, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08480: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08481: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '10x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08482: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '01x0011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08483: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '01x0011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08484: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [3, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08485: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [3, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08486: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08487: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '100x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08488: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '010x011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08489: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '010x011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08490: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [4, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08491: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [4, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08492: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08493: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08494: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '0100x11100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08495: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '0100x11100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08496: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [5, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08497: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [5, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08498: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08499: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '10000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '0100011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08500: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '01000x1100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08501: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '01000x1100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08502: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [6, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08503: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [6, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08504: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08505: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '100001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
08506: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '010000x100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
08507: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '010000x100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08508: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [7, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08509: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [7, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08510: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08511: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
08512: Output = NZ  Instr=D7 ADD B0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '0100001x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
08513: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '0100001x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08514: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [8, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08515: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [8, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08516: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08517: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '10000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '0100001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08518: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '01000011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08519: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '01000011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08520: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [9, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08521: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [9, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08522: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08523: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '100001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08524: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '010000111x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08525: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '010000111x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08526: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [10, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08527: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [10, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08528: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08529: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08530: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '0100001110x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08531: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '0100001110x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08532: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [11, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08533: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [11, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08534: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08535: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '10000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08536: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '01000011100x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08537: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '01000011100x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08538: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [12, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08539: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [12, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08540: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08541: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '100001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08542: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '010000111000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08543: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '010000111000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08544: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [13, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08545: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [13, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08546: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08547: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08548: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '0100001110000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08549: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '0100001110000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08550: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [14, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08551: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [14, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08552: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08553: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '10000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08554: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '01000011100000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08555: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '01000011100000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08556: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [15, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08557: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [15, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08558: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08559: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '100001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08560: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '010000111000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08561: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '010000111000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08562: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [16, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08563: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [16, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08564: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08565: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08566: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '0100001110000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08567: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '0100001110000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08568: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [17, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08569: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [17, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08570: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08571: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '10000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08572: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '01000011100000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08573: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '01000011100000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08574: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08575: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08576: Output = Z  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08577: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08578: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08579: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08580: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08581: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08582: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08583: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08584: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08585: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08586: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08587: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08588: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08589: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08590: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08591: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08592: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08593: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08594: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08595: Output = Z  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08596: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08597: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [16, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08598: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [15, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08599: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [14, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08600: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [13, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08601: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [12, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08602: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [11, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08603: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08604: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [9, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08605: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [8, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08606: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [7, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08607: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [6, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08608: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [5, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08609: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [4, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08610: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [3, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08611: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [2, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08612: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [1, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08613: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08614: Output = Z  Instr=D1 TDEC R4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08615: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08616: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08617: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08618: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08619: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08620: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08621: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08622: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08623: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08624: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08625: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08626: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08627: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08628: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08629: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08630: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08631: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08632: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08633: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08634: Output = Z  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08635: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08636: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08637: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08638: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08639: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08640: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08641: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08642: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08643: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08644: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08645: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08646: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08647: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08648: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08649: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08650: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08651: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08652: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08653: Output = Z  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08654: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08655: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08656: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, 'x100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08657: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, 'x100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08658: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [1, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08659: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [1, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08660: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08661: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08662: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1x00001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08663: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1x00001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08664: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [2, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08665: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [2, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08666: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08667: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '10x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08668: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '11x0001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08669: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '11x0001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08670: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [3, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08671: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [3, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08672: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08673: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '100x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08674: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '110x001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08675: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '110x001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08676: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [4, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08677: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [4, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08678: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08679: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08680: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1100x01110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08681: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1100x01110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08682: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [5, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08683: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [5, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08684: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08685: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '10000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '1100001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08686: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '11000x1110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08687: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '11000x1110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '1100011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08688: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [6, '1100011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08689: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [6, '1100011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08690: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '1100011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08691: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '1100011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '100001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '1100011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '1100011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08692: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '110001x110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08693: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '110001x110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '1100010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08694: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [7, '1100010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08695: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [7, '1100010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08696: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1100010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08697: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1100010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1100010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1100010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
08698: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1100010x10000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
08699: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1100010x10000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1100010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08700: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [8, '1100010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08701: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [8, '1100010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08702: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '1100010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08703: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '1100010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '10000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '1100010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08704: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '11000101x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08705: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '11000101x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '1100010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08706: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [9, '1100010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08707: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [9, '1100010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08708: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '1100010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08709: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '1100010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '100001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '1100010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08710: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '110001010x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08711: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '110001010x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08712: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [10, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08713: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [10, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08714: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08715: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08716: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1100010101x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08717: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1100010101x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08718: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [11, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08719: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [11, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08720: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08721: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '10000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08722: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '11000101010x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08723: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '11000101010x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08724: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [12, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08725: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [12, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08726: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08727: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '100001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08728: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '110001010100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08729: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '110001010100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08730: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [13, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08731: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [13, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08732: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08733: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08734: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1100010101000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08735: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1100010101000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08736: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [14, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08737: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [14, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08738: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08739: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '10000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08740: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '11000101010000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08741: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '11000101010000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08742: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [15, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08743: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [15, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08744: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08745: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '100001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08746: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '110001010100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08747: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '110001010100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08748: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [16, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08749: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [16, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08750: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08751: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08752: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1100010101000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08753: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1100010101000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08754: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [17, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08755: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [17, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08756: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08757: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '10000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08758: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '11000101010000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08759: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '11000101010000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08760: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08761: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08762: Output = Z  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08763: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08764: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08765: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08766: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08767: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08768: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08769: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08770: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08771: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08772: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08773: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08774: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08775: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08776: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08777: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08778: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08779: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08780: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08781: Output = Z  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08782: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08783: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [16, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08784: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [15, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08785: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [14, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08786: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [13, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08787: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [12, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08788: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [11, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08789: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08790: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [9, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08791: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [8, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08792: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [7, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08793: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [6, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08794: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [5, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08795: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [4, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08796: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [3, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08797: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [2, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08798: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [1, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08799: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08800: Output = Z  Instr=D1 TDEC R4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08801: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08802: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08803: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08804: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08805: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08806: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08807: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08808: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08809: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08810: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08811: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08812: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08813: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08814: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08815: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08816: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08817: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08818: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08819: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08820: Output = Z  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08821: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08822: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08823: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08824: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08825: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08826: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08827: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08828: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08829: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08830: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08831: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08832: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08833: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08834: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08835: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08836: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08837: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08838: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08839: Output = Z  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08840: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08841: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08842: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, 'x100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08843: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, 'x100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08844: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [1, '0100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08845: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [1, '0100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08846: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '0100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08847: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '0100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '0100010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08848: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '0x00010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08849: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '0x00010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08850: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [2, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08851: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [2, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08852: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08853: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '10x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08854: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '00x0010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08855: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '00x0010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08856: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [3, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08857: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [3, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08858: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08859: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '100x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08860: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '001x010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08861: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '001x010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08862: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [4, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08863: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [4, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08864: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08865: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08866: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '0010x10101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08867: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '0010x10101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08868: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [5, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08869: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [5, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08870: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08871: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '10000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '0010010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08872: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '00100x0101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
08873: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '00100x0101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08874: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [6, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08875: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [6, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08876: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08877: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '100001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
08878: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '001000x101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
08879: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '001000x101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08880: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [7, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08881: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [7, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08882: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08883: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
08884: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '0010000x01000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
08885: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '0010000x01000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08886: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [8, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08887: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [8, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08888: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08889: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '10000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '0010000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08890: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '00100001x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
08891: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '00100001x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08892: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [9, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08893: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [9, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08894: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08895: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '100001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08896: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '001000011x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08897: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '001000011x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08898: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [10, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08899: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [10, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08900: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08901: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08902: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '0010000111x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08903: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '0010000111x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08904: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [11, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08905: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [11, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08906: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08907: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '10000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08908: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '00100001110x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08909: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '00100001110x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08910: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [12, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08911: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [12, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08912: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08913: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '100001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08914: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '001000011100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08915: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '001000011100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08916: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [13, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08917: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [13, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08918: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08919: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08920: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '0010000111000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08921: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '0010000111000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08922: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [14, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08923: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [14, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08924: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08925: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '10000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08926: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '00100001110000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08927: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '00100001110000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08928: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [15, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08929: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [15, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08930: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08931: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '100001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08932: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '001000011100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08933: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '001000011100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08934: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [16, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08935: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [16, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08936: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08937: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08938: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '0010000111000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08939: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '0010000111000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08940: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [17, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08941: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [17, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08942: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08943: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '10000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08944: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '00100001110000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08945: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '00100001110000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08946: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08947: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08948: Output = Z  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08949: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08950: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08951: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08952: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08953: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08954: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08955: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08956: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08957: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08958: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08959: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08960: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08961: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08962: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08963: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08964: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08965: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08966: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08967: Output = Z  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08968: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08969: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [16, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08970: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [15, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08971: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [14, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08972: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [13, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08973: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [12, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08974: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [11, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08975: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08976: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [9, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08977: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [8, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08978: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [7, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08979: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [6, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08980: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [5, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08981: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [4, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08982: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [3, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08983: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [2, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08984: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [1, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08985: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08986: Output = Z  Instr=D1 TDEC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08987: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08988: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08989: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08990: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08991: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08992: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08993: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08994: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08995: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08996: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08997: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08998: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
08999: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09000: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09001: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09002: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09003: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09004: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09005: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09006: Output = Z  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09007: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09008: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09009: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09010: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09011: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09012: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09013: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09014: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09015: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09016: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09017: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09018: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09019: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09020: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09021: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09022: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09023: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09024: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09025: Output = Z  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09026: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09027: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '0010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
09028: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, 'x010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
09029: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, 'x010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09030: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [1, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09031: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [1, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09032: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09033: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09034: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1x10000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09035: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1x10000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09036: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [2, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09037: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [2, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09038: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09039: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '10x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09040: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '10x0000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09041: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '10x0000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09042: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [3, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09043: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [3, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09044: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09045: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '100x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09046: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '101x000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09047: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '101x000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09048: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [4, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09049: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [4, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09050: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09051: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09052: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1010x00111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09053: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1010x00111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09054: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [5, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09055: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [5, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09056: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09057: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '10000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '1010000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
09058: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '10100x0111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
09059: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '10100x0111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '1010010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09060: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [6, '1010010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09061: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [6, '1010010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09062: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '1010010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09063: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '1010010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '100001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '1010010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '1010010111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
09064: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '101001x111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
09065: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '101001x111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '1010011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09066: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [7, '1010011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09067: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [7, '1010011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09068: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1010011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09069: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1010011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1010011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1010011111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
09070: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1010011x11000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
09071: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1010011x11000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1010011011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09072: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [8, '1010011011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09073: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [8, '1010011011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09074: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '1010011011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09075: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '1010011011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '10000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '1010011011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09076: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '10100110x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09077: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '10100110x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '1010011001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09078: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [9, '1010011001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09079: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [9, '1010011001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09080: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '1010011001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09081: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '1010011001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '100001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '1010011001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09082: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '101001100x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09083: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '101001100x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '1010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09084: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [10, '1010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09085: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [10, '1010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09086: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09087: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1010011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09088: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1010011000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09089: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1010011000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09090: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [11, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09091: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [11, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09092: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09093: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '10000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09094: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '10100110001x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09095: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '10100110001x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09096: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [12, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09097: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [12, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09098: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09099: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '100001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09100: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '101001100010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09101: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '101001100010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09102: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [13, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09103: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [13, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09104: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09105: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09106: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1010011000100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09107: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1010011000100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09108: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [14, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09109: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [14, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09110: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09111: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '10000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09112: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '10100110001000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09113: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '10100110001000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09114: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [15, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09115: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [15, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09116: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09117: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '100001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09118: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '101001100010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09119: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '101001100010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09120: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [16, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09121: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [16, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09122: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09123: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09124: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1010011000100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09125: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1010011000100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09126: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [17, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09127: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [17, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09128: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09129: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '10000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09130: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '10100110001000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09131: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '10100110001000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09132: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09133: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09134: Output = Z  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09135: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09136: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09137: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09138: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09139: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09140: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09141: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09142: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09143: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09144: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09145: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09146: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09147: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09148: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09149: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09150: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09151: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09152: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09153: Output = Z  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09154: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09155: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [16, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09156: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [15, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09157: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [14, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09158: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [13, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09159: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [12, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09160: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [11, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09161: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09162: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [9, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09163: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [8, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09164: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [7, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09165: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [6, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09166: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [5, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09167: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [4, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09168: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [3, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09169: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [2, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09170: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [1, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09171: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09172: Output = Z  Instr=D1 TDEC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09173: Output = Z  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09174: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09175: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09176: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09177: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09178: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09179: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09180: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09181: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09182: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09183: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09184: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09185: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09186: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09187: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09188: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09189: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09190: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09191: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09192: Output = Z  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09193: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09194: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09195: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09196: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09197: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09198: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09199: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09200: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09201: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09202: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09203: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09204: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09205: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09206: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09207: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09208: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09209: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09210: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09211: Output = Z  Instr=COMP NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09212: Output = Z  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09213: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09214: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09215: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 5, 'T4': [1, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09216: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09217: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [1, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09218: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 5, 'T4': [2, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09219: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09220: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [2, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09221: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 5, 'T4': [3, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09222: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09223: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [3, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09224: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 5, 'T4': [4, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09225: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09226: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [4, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09227: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 5, 'T4': [5, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09228: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09229: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [5, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09230: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 5, 'T4': [6, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09231: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09232: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [6, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09233: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 5, 'T4': [7, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09234: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09235: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [7, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09236: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 5, 'T4': [8, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09237: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09238: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [8, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09239: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 5, 'T4': [9, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09240: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09241: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [9, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09242: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09243: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09244: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09245: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 5, 'T4': [11, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09246: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09247: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [11, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09248: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 5, 'T4': [12, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09249: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09250: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [12, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09251: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 5, 'T4': [13, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09252: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09253: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [13, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09254: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 5, 'T4': [14, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09255: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09256: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [14, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09257: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 5, 'T4': [15, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09258: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09259: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [15, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09260: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 5, 'T4': [16, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09261: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09262: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [16, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09263: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 5, 'T4': [17, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09264: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09265: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09266: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09267: Output = Z  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09268: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '000010011000000000x'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09269: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '101001100010000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [18, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09270: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09271: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09272: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '00001001100000000x0'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09273: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '10100110001000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [17, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09274: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [16, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09275: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [16, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09276: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [16, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000x00'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [16, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09277: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [16, '1010011000100000x00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [16, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09278: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [15, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09279: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [15, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09280: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [15, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '000010011000000x000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [15, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09281: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [15, '101001100010000x000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [15, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09282: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [14, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09283: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [14, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09284: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [14, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '00001001100000x0000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [14, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09285: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [14, '10100110001000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [14, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09286: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [13, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09287: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [13, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09288: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [13, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000x00000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [13, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09289: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [13, '1010011000100x00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [13, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09290: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [12, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09291: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [12, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09292: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [12, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '000010011000x000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [12, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09293: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [12, '101001100010x000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [12, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09294: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [11, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09295: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [11, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09296: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [11, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '00001001100x0000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [11, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09297: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [11, '10100110001x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [11, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09298: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09299: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09300: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110x00000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09301: Output = NZ  Instr=E9 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1010011000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09302: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09303: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09304: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09305: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09306: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09307: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09308: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09309: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09310: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09311: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09312: Output = Z  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [10, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09313: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [9, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09314: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [8, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09315: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [7, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09316: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [6, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09317: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [5, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09318: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [4, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09319: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [3, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09320: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [2, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09321: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [1, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09322: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09323: Output = Z  Instr=E11 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 5, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09324: Output = NZ  Instr=EVL NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09325: Output = Z  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09326: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09327: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09328: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09329: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09330: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09331: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09332: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09333: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09334: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09335: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09336: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09337: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09338: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09339: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09340: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09341: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09342: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09343: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09344: Output = Z  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09345: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09346: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09347: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09348: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09349: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09350: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09351: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09352: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09353: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09354: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09355: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09356: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09357: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09358: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09359: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09360: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09361: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09362: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09363: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09364: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '1010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09365: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, 'x010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09366: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [1, '0010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09367: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09368: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0x10011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09369: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [2, '0010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09370: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0010011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09371: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '00x0011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09372: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [3, '0000011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09373: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09374: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '000x011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09375: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [4, '0000011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09376: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09377: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000x11000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09378: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [5, '0000011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09379: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000011000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09380: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '00000x1000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09381: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [6, '0000001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09382: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000001000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09383: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '000000x000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09384: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [7, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09385: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09386: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000000x00100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09387: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [8, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09388: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09389: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '00000000x0100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09390: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [9, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09391: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09392: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '000000000x100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09393: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [10, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09394: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000000000100000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09395: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000000000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09396: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09397: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09398: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '00000000000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09399: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09400: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09401: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '000000000000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09402: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09403: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09404: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000000000000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09405: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09406: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09407: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '00000000000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09408: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09409: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09410: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '000000000000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09411: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09412: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09413: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000000000000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09414: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09415: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09416: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '00000000000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09417: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09418: Output = Z  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09419: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09420: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09421: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09422: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09423: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09424: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09425: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09426: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09427: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09428: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [8, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09429: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [7, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09430: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [6, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09431: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [5, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09432: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [4, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09433: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [3, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09434: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09435: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09436: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09437: Output = Z  Instr=B5 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09438: Output = Z  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09439: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09440: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09441: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09442: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09443: Output = Z  Instr=B7 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09444: Output = NZ  Instr=B7 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09445: Output = NZ  Instr=B7 INC R3; regs={'R4': 1, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 1, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09446: Output = NZ  Instr=B7 INC R3; regs={'R4': 2, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 2, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09447: Output = NZ  Instr=B7 INC R3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09448: Output = Z  Instr=B8 NOP; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09449: Output = Z  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09450: Output = NZ  Instr=B9 INC R1; regs={'R4': 4, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09451: Output = NZ  Instr=B9 INC R1; regs={'R4': 4, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09452: Output = NZ  Instr=B9 INC R1; regs={'R4': 4, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09453: Output = NZ  Instr=B9 INC R1; regs={'R4': 4, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09454: Output = NZ  Instr=B9 INC R1; regs={'R4': 4, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09455: Output = NZ  Instr=B9 INC R1; regs={'R4': 4, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09456: Output = NZ  Instr=B9 INC R1; regs={'R4': 4, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09457: Output = NZ  Instr=B9 INC R1; regs={'R4': 4, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09458: Output = NZ  Instr=B9 INC R1; regs={'R4': 4, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09459: Output = NZ  Instr=B9 INC R1; regs={'R4': 4, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09460: Output = NZ  Instr=B9 INC R1; regs={'R4': 4, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09461: Output = NZ  Instr=B9 INC R1; regs={'R4': 4, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09462: Output = NZ  Instr=B9 INC R1; regs={'R4': 4, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09463: Output = NZ  Instr=B9 INC R1; regs={'R4': 4, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09464: Output = NZ  Instr=B9 INC R1; regs={'R4': 4, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09465: Output = NZ  Instr=B9 INC R1; regs={'R4': 4, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09466: Output = NZ  Instr=B9 INC R1; regs={'R4': 4, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09467: Output = NZ  Instr=B9 INC R1; regs={'R4': 4, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 4, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09468: Output = Z  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09469: Output = NZ  Instr=B10 INC R0; regs={'R4': 4, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 4, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09470: Output = NZ  Instr=B10 INC R0; regs={'R4': 4, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 4, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09471: Output = NZ  Instr=B10 INC R0; regs={'R4': 4, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 4, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09472: Output = NZ  Instr=B10 INC R0; regs={'R4': 4, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 4, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09473: Output = NZ  Instr=B10 INC R0; regs={'R4': 4, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 4, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09474: Output = NZ  Instr=B10 INC R0; regs={'R4': 4, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 4, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09475: Output = NZ  Instr=B10 INC R0; regs={'R4': 4, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 4, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09476: Output = NZ  Instr=B10 INC R0; regs={'R4': 4, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 4, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09477: Output = NZ  Instr=B10 INC R0; regs={'R4': 4, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 4, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09478: Output = NZ  Instr=B10 INC R0; regs={'R4': 4, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 4, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09479: Output = NZ  Instr=B10 INC R0; regs={'R4': 4, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 4, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09480: Output = NZ  Instr=B10 INC R0; regs={'R4': 4, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 4, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09481: Output = NZ  Instr=B10 INC R0; regs={'R4': 4, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 4, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09482: Output = NZ  Instr=B10 INC R0; regs={'R4': 4, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 4, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09483: Output = NZ  Instr=B10 INC R0; regs={'R4': 4, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 4, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09484: Output = NZ  Instr=B10 INC R0; regs={'R4': 4, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 4, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09485: Output = NZ  Instr=B10 INC R0; regs={'R4': 4, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 4, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09486: Output = NZ  Instr=B10 INC R0; regs={'R4': 4, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09487: Output = Z  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09488: Output = NZ  Instr=B12 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09489: Output = NZ  Instr=B13 READ T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09490: Output = Z  Instr=B14 RESET T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, 'x011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09491: Output = NZ  Instr=B15 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09492: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09493: Output = NZ  Instr=B12 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09494: Output = Z  Instr=B13 READ T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09495: Output = Z  Instr=B14 RESET T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [1, '0x11101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09496: Output = NZ  Instr=B15 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09497: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09498: Output = NZ  Instr=B12 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09499: Output = Z  Instr=B13 READ T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09500: Output = NZ  Instr=B14 SET T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [2, '00x1101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09501: Output = NZ  Instr=B15 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09502: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09503: Output = NZ  Instr=B12 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09504: Output = Z  Instr=B13 READ T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09505: Output = NZ  Instr=B14 SET T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [3, '001x101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09506: Output = NZ  Instr=B15 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [3, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09507: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09508: Output = NZ  Instr=B12 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09509: Output = Z  Instr=B13 READ T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09510: Output = NZ  Instr=B14 SET T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011x01100000000000'], 'T3': [4, '0011x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09511: Output = NZ  Instr=B15 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [4, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09512: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09513: Output = NZ  Instr=B12 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09514: Output = NZ  Instr=B13 READ T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09515: Output = Z  Instr=B14 RESET T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [5, '00111x1100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09516: Output = NZ  Instr=B15 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09517: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09518: Output = NZ  Instr=B12 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09519: Output = NZ  Instr=B13 READ T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09520: Output = NZ  Instr=B14 SET T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [6, '001110x100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09521: Output = NZ  Instr=B15 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09522: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09523: Output = NZ  Instr=B12 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09524: Output = NZ  Instr=B13 READ T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09525: Output = NZ  Instr=B14 SET T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101x00000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09526: Output = NZ  Instr=B15 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09527: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09528: Output = NZ  Instr=B12 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09529: Output = Z  Instr=B13 READ T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09530: Output = Z  Instr=B14 RESET T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [8, '00111011x0000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09531: Output = NZ  Instr=B15 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09532: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09533: Output = NZ  Instr=B12 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09534: Output = Z  Instr=B13 READ T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09535: Output = Z  Instr=B14 RESET T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [9, '001110110x000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09536: Output = NZ  Instr=B15 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09537: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09538: Output = NZ  Instr=B12 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09539: Output = Z  Instr=B13 READ T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09540: Output = Z  Instr=B14 RESET T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100x00000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09541: Output = NZ  Instr=B15 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09542: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09543: Output = NZ  Instr=B12 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09544: Output = Z  Instr=B13 READ T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09545: Output = Z  Instr=B14 RESET T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [11, '00111011000x0000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09546: Output = NZ  Instr=B15 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09547: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09548: Output = NZ  Instr=B12 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09549: Output = Z  Instr=B13 READ T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09550: Output = Z  Instr=B14 RESET T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [12, '001110110000x000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09551: Output = NZ  Instr=B15 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09552: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09553: Output = NZ  Instr=B12 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09554: Output = Z  Instr=B13 READ T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09555: Output = Z  Instr=B14 RESET T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000x00000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09556: Output = NZ  Instr=B15 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09557: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09558: Output = NZ  Instr=B12 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09559: Output = Z  Instr=B13 READ T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09560: Output = Z  Instr=B14 RESET T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [14, '00111011000000x0000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09561: Output = NZ  Instr=B15 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09562: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09563: Output = NZ  Instr=B12 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09564: Output = Z  Instr=B13 READ T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09565: Output = Z  Instr=B14 RESET T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [15, '001110110000000x000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09566: Output = NZ  Instr=B15 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09567: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09568: Output = NZ  Instr=B12 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09569: Output = Z  Instr=B13 READ T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09570: Output = Z  Instr=B14 RESET T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000x00'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09571: Output = NZ  Instr=B15 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09572: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09573: Output = NZ  Instr=B12 READ T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09574: Output = Z  Instr=B13 READ T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09575: Output = Z  Instr=B14 RESET T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [17, '00111011000000000x0'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09576: Output = NZ  Instr=B15 INC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09577: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09578: Output = Z  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09579: Output = NZ  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09580: Output = NZ  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09581: Output = NZ  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09582: Output = NZ  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09583: Output = NZ  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09584: Output = NZ  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09585: Output = NZ  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09586: Output = NZ  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09587: Output = NZ  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09588: Output = NZ  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09589: Output = NZ  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09590: Output = NZ  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09591: Output = NZ  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09592: Output = NZ  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09593: Output = NZ  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09594: Output = NZ  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09595: Output = NZ  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09596: Output = NZ  Instr=B16 DEC T2; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09597: Output = Z  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09598: Output = NZ  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09599: Output = NZ  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09600: Output = NZ  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09601: Output = NZ  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09602: Output = NZ  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09603: Output = NZ  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09604: Output = NZ  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09605: Output = NZ  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09606: Output = NZ  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09607: Output = NZ  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09608: Output = NZ  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09609: Output = NZ  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09610: Output = NZ  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09611: Output = NZ  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09612: Output = NZ  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09613: Output = NZ  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09614: Output = NZ  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09615: Output = NZ  Instr=B17 DEC T3; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09616: Output = Z  Instr=ADD NOP; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09617: Output = Z  Instr=C1 TDEC R4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09618: Output = NZ  Instr=C2 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09619: Output = Z  Instr=C4 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09620: Output = Z  Instr=C1 TDEC R4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09621: Output = NZ  Instr=C2 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09622: Output = NZ  Instr=C3 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09623: Output = NZ  Instr=C2 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09624: Output = Z  Instr=C4 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09625: Output = NZ  Instr=C4 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09626: Output = Z  Instr=C1 TDEC R4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09627: Output = NZ  Instr=C2 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09628: Output = Z  Instr=C4 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09629: Output = Z  Instr=C1 TDEC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09630: Output = NZ  Instr=C2 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09631: Output = NZ  Instr=C3 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09632: Output = NZ  Instr=C2 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09633: Output = NZ  Instr=C3 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09634: Output = NZ  Instr=C2 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09635: Output = NZ  Instr=C3 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x1101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0001101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09636: Output = NZ  Instr=C2 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0001101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09637: Output = NZ  Instr=C3 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '000x101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09638: Output = NZ  Instr=C2 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09639: Output = NZ  Instr=C3 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000x01100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000001100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09640: Output = NZ  Instr=C2 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000001100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09641: Output = Z  Instr=C4 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '00000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09642: Output = NZ  Instr=C4 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09643: Output = NZ  Instr=C4 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09644: Output = NZ  Instr=C4 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09645: Output = NZ  Instr=C4 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09646: Output = NZ  Instr=C4 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09647: Output = Z  Instr=C1 TDEC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09648: Output = Z  Instr=C5 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09649: Output = Z  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09650: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09651: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09652: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09653: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09654: Output = Z  Instr=C7 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 4, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09655: Output = NZ  Instr=C7 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09656: Output = NZ  Instr=C7 INC R3; regs={'R4': 1, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 1, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09657: Output = NZ  Instr=C7 INC R3; regs={'R4': 2, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 2, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09658: Output = NZ  Instr=C7 INC R3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09659: Output = Z  Instr=MUL NOP; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09660: Output = Z  Instr=D1 TDEC R4; regs={'R4': 4, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09661: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09662: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09663: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09664: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09665: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09666: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09667: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09668: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09669: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09670: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09671: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09672: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09673: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09674: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09675: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09676: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09677: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09678: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09679: Output = NZ  Instr=D2 INC R1; regs={'R4': 3, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 3, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09680: Output = Z  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09681: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09682: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09683: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09684: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09685: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09686: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09687: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09688: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09689: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09690: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09691: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09692: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09693: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09694: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09695: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09696: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09697: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09698: Output = NZ  Instr=D3 INC R0; regs={'R4': 3, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09699: Output = Z  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09700: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09701: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09702: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, 'x000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09703: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, 'x000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09704: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09705: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09706: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09707: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09708: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0x00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09709: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0x00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09710: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09711: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09712: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09713: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09714: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '00x0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09715: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '00x0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09716: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [3, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09717: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [3, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09718: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09719: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '000x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09720: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '000x000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09721: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '000x000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09722: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [4, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09723: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [4, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09724: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09725: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09726: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000x00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09727: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000x00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09728: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [5, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09729: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [5, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09730: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09731: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '00000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
09732: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '00000x0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
09733: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '00000x0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09734: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [6, '0000010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09735: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [6, '0000010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09736: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09737: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '000001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000010000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
09738: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '000001x000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
09739: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '000001x000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09740: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [7, '0000011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09741: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [7, '0000011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09742: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09743: Output = NZ  Instr=D6 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000011000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
09744: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000011x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
09745: Output = NZ  Instr=D8 SET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000011x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09746: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [8, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09747: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [8, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09748: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09749: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '00000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09750: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '00000111x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09751: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '00000111x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09752: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [9, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09753: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [9, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09754: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09755: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '000001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09756: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '000001110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09757: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '000001110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09758: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [10, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09759: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [10, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09760: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09761: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09762: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000011100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09763: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000011100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09764: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [11, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09765: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [11, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09766: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09767: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '00000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09768: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '00000111000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09769: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '00000111000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09770: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [12, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09771: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [12, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09772: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09773: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '000001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09774: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '000001110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09775: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '000001110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09776: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [13, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09777: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [13, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09778: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09779: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09780: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000011100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09781: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000011100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09782: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [14, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09783: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [14, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09784: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09785: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '00000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09786: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '00000111000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09787: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '00000111000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09788: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [15, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09789: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [15, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09790: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09791: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '000001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09792: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '000001110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09793: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '000001110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09794: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [16, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09795: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [16, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09796: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09797: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09798: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000011100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09799: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000011100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09800: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [17, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09801: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [17, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09802: Output = NZ  Instr=D5 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09803: Output = Z  Instr=D6 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '00000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09804: Output = Z  Instr=D7 ADD B1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '00000111000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09805: Output = Z  Instr=D8 RESET T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '00000111000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09806: Output = NZ  Instr=D8A INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09807: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09808: Output = Z  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09809: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09810: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09811: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09812: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09813: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09814: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09815: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09816: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09817: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09818: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09819: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09820: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09821: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09822: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09823: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09824: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09825: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09826: Output = NZ  Instr=D9 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09827: Output = Z  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09828: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09829: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [16, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09830: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [15, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09831: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [14, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09832: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [13, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09833: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [12, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09834: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [11, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09835: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [10, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09836: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09837: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [8, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09838: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [7, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09839: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [6, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09840: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [5, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09841: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [4, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09842: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [3, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09843: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [2, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09844: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [1, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09845: Output = NZ  Instr=D10 DEC T4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09846: Output = Z  Instr=D1 TDEC R4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09847: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09848: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09849: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09850: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09851: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09852: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09853: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09854: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09855: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09856: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09857: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09858: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09859: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09860: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09861: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09862: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09863: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09864: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09865: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09866: Output = Z  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09867: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09868: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09869: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09870: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09871: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09872: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09873: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09874: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09875: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09876: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09877: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09878: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09879: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09880: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09881: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09882: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09883: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09884: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09885: Output = Z  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09886: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09887: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09888: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, 'x000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09889: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, 'x000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09890: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [1, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09891: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [1, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09892: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09893: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09894: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0x00011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09895: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0x00011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09896: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [2, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09897: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [2, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09898: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09899: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09900: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '00x0011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09901: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '00x0011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09902: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [3, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09903: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [3, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09904: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09905: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '000x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09906: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '000x011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09907: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '000x011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09908: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [4, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09909: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [4, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09910: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09911: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09912: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000x11100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09913: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000x11100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09914: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [5, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09915: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [5, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09916: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09917: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '00000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000011100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
09918: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '00000x1100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
09919: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '00000x1100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09920: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [6, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09921: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [6, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09922: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09923: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '000001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
09924: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '000000x100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
09925: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '000000x100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09926: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [7, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09927: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [7, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09928: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09929: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
09930: Output = NZ  Instr=D7 ADD B0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000001x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
09931: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000001x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09932: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [8, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09933: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [8, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09934: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09935: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '00000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000001100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09936: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '00000011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
09937: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '00000011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09938: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [9, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09939: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [9, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09940: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09941: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '000001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09942: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '000000111x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09943: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '000000111x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09944: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [10, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09945: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [10, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09946: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09947: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09948: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000001110x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09949: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000001110x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09950: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [11, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09951: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [11, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09952: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09953: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '00000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09954: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '00000011100x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09955: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '00000011100x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09956: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [12, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09957: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [12, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09958: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09959: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '000001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09960: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '000000111000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09961: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '000000111000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09962: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [13, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09963: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [13, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09964: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09965: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09966: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000001110000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09967: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000001110000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09968: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [14, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09969: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [14, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09970: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09971: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '00000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09972: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '00000011100000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09973: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '00000011100000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09974: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [15, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09975: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [15, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09976: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09977: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '000001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09978: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '000000111000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09979: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '000000111000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09980: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [16, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09981: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [16, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09982: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09983: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09984: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000001110000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09985: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000001110000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09986: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [17, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09987: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [17, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09988: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09989: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '00000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09990: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '00000011100000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09991: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '00000011100000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09992: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09993: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09994: Output = Z  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09995: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09996: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09997: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09998: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
09999: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10000: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10001: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10002: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10003: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10004: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10005: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10006: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10007: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10008: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10009: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10010: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10011: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10012: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10013: Output = Z  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10014: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10015: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [16, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10016: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [15, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10017: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [14, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10018: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [13, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10019: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [12, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10020: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [11, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10021: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [10, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10022: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10023: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [8, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10024: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [7, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10025: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [6, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10026: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [5, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10027: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [4, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10028: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [3, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10029: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [2, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10030: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [1, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10031: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10032: Output = Z  Instr=D1 TDEC R4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10033: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10034: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10035: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10036: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10037: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10038: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10039: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10040: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10041: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10042: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10043: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10044: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10045: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10046: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10047: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10048: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10049: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10050: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10051: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10052: Output = Z  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10053: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10054: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10055: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10056: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10057: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10058: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10059: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10060: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10061: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10062: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10063: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10064: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10065: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10066: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10067: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10068: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10069: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10070: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10071: Output = Z  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10072: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10073: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10074: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, 'x000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10075: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, 'x000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10076: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [1, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10077: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [1, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10078: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10079: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10080: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0x00001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10081: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0x00001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10082: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [2, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10083: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [2, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10084: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10085: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10086: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '00x0001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10087: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '00x0001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10088: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [3, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10089: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [3, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10090: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10091: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '000x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10092: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '000x001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10093: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '000x001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10094: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [4, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10095: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [4, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10096: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10097: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10098: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000x01110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10099: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000x01110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10100: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [5, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10101: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [5, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10102: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10103: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '00000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000001110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10104: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '00000x1110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10105: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '00000x1110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10106: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [6, '0000011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10107: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [6, '0000011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10108: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10109: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '000001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000011110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10110: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '000001x110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10111: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '000001x110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10112: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [7, '0000010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10113: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [7, '0000010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10114: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10115: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
10116: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000010x10000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
10117: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000010x10000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10118: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [8, '0000010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10119: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [8, '0000010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10120: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10121: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '00000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10122: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '00000101x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10123: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '00000101x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10124: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [9, '0000010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10125: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [9, '0000010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10126: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10127: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '000001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000010100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10128: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '000001010x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10129: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '000001010x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10130: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [10, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10131: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [10, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10132: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10133: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10134: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000010101x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10135: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000010101x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10136: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [11, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10137: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [11, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10138: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10139: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '00000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10140: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '00000101010x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10141: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '00000101010x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10142: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [12, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10143: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [12, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10144: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10145: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '000001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10146: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '000001010100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10147: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '000001010100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10148: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [13, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10149: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [13, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10150: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10151: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10152: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000010101000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10153: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000010101000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10154: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [14, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10155: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [14, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10156: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10157: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '00000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10158: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '00000101010000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10159: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '00000101010000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10160: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [15, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10161: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [15, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10162: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10163: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '000001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10164: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '000001010100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10165: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '000001010100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10166: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [16, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10167: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [16, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10168: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10169: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10170: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000010101000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10171: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000010101000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10172: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [17, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10173: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [17, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10174: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10175: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '00000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10176: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '00000101010000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10177: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '00000101010000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10178: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10179: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10180: Output = Z  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10181: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10182: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10183: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10184: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10185: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10186: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10187: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10188: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10189: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10190: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10191: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10192: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10193: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10194: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10195: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10196: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10197: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10198: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10199: Output = Z  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10200: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10201: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [16, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10202: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [15, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10203: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [14, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10204: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [13, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10205: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [12, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10206: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [11, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10207: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [10, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10208: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10209: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [8, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10210: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [7, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10211: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [6, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10212: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [5, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10213: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [4, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10214: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [3, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10215: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [2, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10216: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [1, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10217: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10218: Output = Z  Instr=D1 TDEC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10219: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10220: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10221: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10222: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10223: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10224: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10225: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10226: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10227: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10228: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10229: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10230: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10231: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10232: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10233: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10234: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10235: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10236: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10237: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10238: Output = Z  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10239: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10240: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10241: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10242: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10243: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10244: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10245: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10246: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10247: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10248: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10249: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10250: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10251: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10252: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10253: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10254: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10255: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10256: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10257: Output = Z  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10258: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10259: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10260: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, 'x000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10261: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, 'x000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10262: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [1, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10263: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [1, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10264: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10265: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10266: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0x00010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10267: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0x00010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10268: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [2, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10269: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [2, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10270: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10271: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10272: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '00x0010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10273: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '00x0010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10274: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [3, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10275: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [3, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10276: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10277: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '000x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10278: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '000x010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10279: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '000x010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10280: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [4, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10281: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [4, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10282: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10283: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10284: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000x10101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10285: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000x10101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10286: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [5, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10287: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [5, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10288: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10289: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '00000x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000010101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10290: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '00000x0101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10291: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '00000x0101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10292: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [6, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10293: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [6, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10294: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10295: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '000001x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
10296: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '000000x101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
10297: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '000000x101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10298: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [7, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10299: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [7, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10300: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10301: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
10302: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000000x01000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
10303: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000000x01000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10304: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [8, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10305: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [8, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10306: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10307: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '00000111x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10308: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '00000001x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
10309: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '00000001x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10310: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10311: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10312: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10313: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '000001110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10314: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '000000011x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10315: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '000000011x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10316: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [10, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10317: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [10, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10318: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10319: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10320: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000000111x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10321: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000000111x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10322: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [11, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10323: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [11, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10324: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10325: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '00000111000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10326: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '00000001110x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10327: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '00000001110x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10328: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [12, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10329: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [12, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10330: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10331: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '000001110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10332: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '000000011100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10333: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '000000011100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10334: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [13, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10335: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [13, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10336: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10337: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10338: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000000111000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10339: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000000111000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10340: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [14, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10341: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [14, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10342: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10343: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '00000111000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10344: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '00000001110000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10345: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '00000001110000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10346: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [15, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10347: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [15, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10348: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10349: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '000001110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10350: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '000000011100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10351: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '000000011100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10352: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [16, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10353: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [16, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10354: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10355: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10356: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000000111000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10357: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000000111000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10358: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [17, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10359: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [17, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10360: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10361: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '00000111000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10362: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '00000001110000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10363: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '00000001110000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10364: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10365: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10366: Output = Z  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10367: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10368: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10369: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10370: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10371: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10372: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10373: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10374: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10375: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10376: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10377: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10378: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10379: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10380: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10381: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10382: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10383: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10384: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10385: Output = Z  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10386: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10387: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [16, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10388: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [15, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10389: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [14, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10390: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [13, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10391: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [12, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10392: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [11, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10393: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [10, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10394: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10395: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [8, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10396: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [7, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10397: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [6, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10398: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [5, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10399: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [4, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10400: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [3, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10401: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [2, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10402: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [1, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10403: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10404: Output = Z  Instr=D1 TDEC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10405: Output = Z  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10406: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10407: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10408: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10409: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10410: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10411: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10412: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10413: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10414: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10415: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10416: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10417: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10418: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10419: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10420: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10421: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10422: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10423: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10424: Output = Z  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10425: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10426: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10427: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10428: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10429: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10430: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10431: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10432: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10433: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10434: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10435: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10436: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10437: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10438: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10439: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10440: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10441: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10442: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10443: Output = Z  Instr=COMP NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10444: Output = Z  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10445: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10446: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10447: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 4, 'T4': [1, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10448: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10449: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [1, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10450: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 4, 'T4': [2, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10451: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10452: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [2, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10453: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 4, 'T4': [3, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10454: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10455: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [3, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10456: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 4, 'T4': [4, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10457: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10458: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [4, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10459: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 4, 'T4': [5, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10460: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10461: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [5, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10462: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 4, 'T4': [6, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10463: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10464: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [6, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10465: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 4, 'T4': [7, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10466: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10467: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [7, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10468: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 4, 'T4': [8, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10469: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10470: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [8, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10471: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10472: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10473: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10474: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 4, 'T4': [10, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10475: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10476: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [10, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10477: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 4, 'T4': [11, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10478: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10479: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [11, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10480: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 4, 'T4': [12, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10481: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10482: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [12, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10483: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 4, 'T4': [13, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10484: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10485: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [13, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10486: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 4, 'T4': [14, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10487: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10488: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [14, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10489: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 4, 'T4': [15, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10490: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10491: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [15, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10492: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 4, 'T4': [16, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10493: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10494: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [16, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10495: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 4, 'T4': [17, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10496: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10497: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10498: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10499: Output = Z  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10500: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '000010011000000000x'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10501: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '000000011100000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [18, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10502: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10503: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10504: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '00001001100000000x0'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10505: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '00000001110000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [17, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10506: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [16, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10507: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [16, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10508: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [16, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000x00'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [16, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10509: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [16, '0000000111000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [16, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10510: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [15, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10511: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [15, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10512: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [15, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '000010011000000x000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [15, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10513: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [15, '000000011100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [15, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10514: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [14, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10515: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [14, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10516: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [14, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '00001001100000x0000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [14, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10517: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [14, '00000001110000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [14, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10518: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [13, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10519: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [13, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10520: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [13, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000x00000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [13, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10521: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [13, '0000000111000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [13, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10522: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [12, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10523: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [12, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10524: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [12, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '000010011000x000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [12, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10525: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [12, '000000011100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [12, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10526: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [11, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10527: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [11, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10528: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [11, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '00001001100x0000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [11, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10529: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [11, '00000001110x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [11, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10530: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [10, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10531: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [10, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10532: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [10, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110x00000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [10, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10533: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [10, '0000000111x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [10, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10534: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10535: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10536: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '000010011x000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10537: Output = NZ  Instr=E9 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '000000011x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10538: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10539: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10540: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10541: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10542: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10543: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10544: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10545: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10546: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10547: Output = Z  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [9, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10548: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [8, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10549: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [7, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10550: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [6, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10551: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [5, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10552: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [4, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10553: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [3, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10554: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [2, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10555: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [1, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10556: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10557: Output = Z  Instr=E11 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 4, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10558: Output = NZ  Instr=EVL NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10559: Output = Z  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10560: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10561: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10562: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10563: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10564: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10565: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10566: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10567: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10568: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10569: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10570: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10571: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10572: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10573: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10574: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10575: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10576: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10577: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10578: Output = Z  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10579: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10580: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10581: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10582: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10583: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10584: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10585: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10586: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10587: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10588: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10589: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10590: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10591: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10592: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10593: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10594: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10595: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10596: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10597: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10598: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10599: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, 'x000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10600: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [1, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10601: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10602: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '0x00000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10603: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [2, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10604: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10605: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '00x0000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10606: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [3, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10607: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10608: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '000x000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10609: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [4, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10610: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10611: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '0000x00111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10612: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [5, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10613: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10614: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '00000x0111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10615: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [6, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10616: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10617: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '000000x111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10618: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [7, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10619: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '0000000111000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10620: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '0000000x11000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '0000000011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10621: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [8, '0000000011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10622: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '0000000011000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10623: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '00000000x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '0000000001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10624: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [9, '0000000001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10625: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '0000000001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10626: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '000000000x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10627: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10628: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10629: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '0000000000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10630: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10631: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10632: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '00000000000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10633: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10634: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10635: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '000000000000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10636: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10637: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10638: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '0000000000000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10639: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10640: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10641: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '00000000000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10642: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10643: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10644: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '000000000000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10645: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10646: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10647: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '0000000000000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10648: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10649: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10650: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '00000000000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10651: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10652: Output = Z  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10653: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10654: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10655: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10656: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10657: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10658: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10659: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10660: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10661: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10662: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [8, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10663: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [7, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10664: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [6, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10665: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [5, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10666: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [4, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10667: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [3, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10668: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10669: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10670: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10671: Output = Z  Instr=B5 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10672: Output = Z  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10673: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10674: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10675: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10676: Output = Z  Instr=B7 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10677: Output = NZ  Instr=B7 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10678: Output = NZ  Instr=B7 INC R3; regs={'R4': 1, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 1, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10679: Output = NZ  Instr=B7 INC R3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10680: Output = Z  Instr=B8 NOP; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10681: Output = Z  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10682: Output = NZ  Instr=B9 INC R1; regs={'R4': 3, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10683: Output = NZ  Instr=B9 INC R1; regs={'R4': 3, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10684: Output = NZ  Instr=B9 INC R1; regs={'R4': 3, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10685: Output = NZ  Instr=B9 INC R1; regs={'R4': 3, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10686: Output = NZ  Instr=B9 INC R1; regs={'R4': 3, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10687: Output = NZ  Instr=B9 INC R1; regs={'R4': 3, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10688: Output = NZ  Instr=B9 INC R1; regs={'R4': 3, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10689: Output = NZ  Instr=B9 INC R1; regs={'R4': 3, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10690: Output = NZ  Instr=B9 INC R1; regs={'R4': 3, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10691: Output = NZ  Instr=B9 INC R1; regs={'R4': 3, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10692: Output = NZ  Instr=B9 INC R1; regs={'R4': 3, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10693: Output = NZ  Instr=B9 INC R1; regs={'R4': 3, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10694: Output = NZ  Instr=B9 INC R1; regs={'R4': 3, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10695: Output = NZ  Instr=B9 INC R1; regs={'R4': 3, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10696: Output = NZ  Instr=B9 INC R1; regs={'R4': 3, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10697: Output = NZ  Instr=B9 INC R1; regs={'R4': 3, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10698: Output = NZ  Instr=B9 INC R1; regs={'R4': 3, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10699: Output = NZ  Instr=B9 INC R1; regs={'R4': 3, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 3, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10700: Output = Z  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10701: Output = NZ  Instr=B10 INC R0; regs={'R4': 3, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10702: Output = NZ  Instr=B10 INC R0; regs={'R4': 3, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10703: Output = NZ  Instr=B10 INC R0; regs={'R4': 3, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10704: Output = NZ  Instr=B10 INC R0; regs={'R4': 3, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10705: Output = NZ  Instr=B10 INC R0; regs={'R4': 3, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10706: Output = NZ  Instr=B10 INC R0; regs={'R4': 3, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10707: Output = NZ  Instr=B10 INC R0; regs={'R4': 3, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10708: Output = NZ  Instr=B10 INC R0; regs={'R4': 3, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10709: Output = NZ  Instr=B10 INC R0; regs={'R4': 3, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10710: Output = NZ  Instr=B10 INC R0; regs={'R4': 3, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10711: Output = NZ  Instr=B10 INC R0; regs={'R4': 3, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10712: Output = NZ  Instr=B10 INC R0; regs={'R4': 3, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10713: Output = NZ  Instr=B10 INC R0; regs={'R4': 3, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10714: Output = NZ  Instr=B10 INC R0; regs={'R4': 3, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10715: Output = NZ  Instr=B10 INC R0; regs={'R4': 3, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10716: Output = NZ  Instr=B10 INC R0; regs={'R4': 3, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10717: Output = NZ  Instr=B10 INC R0; regs={'R4': 3, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10718: Output = NZ  Instr=B10 INC R0; regs={'R4': 3, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10719: Output = Z  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10720: Output = NZ  Instr=B12 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10721: Output = Z  Instr=B13 READ T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10722: Output = Z  Instr=B14 RESET T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, 'x011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10723: Output = NZ  Instr=B15 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [0, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10724: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10725: Output = NZ  Instr=B12 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10726: Output = Z  Instr=B13 READ T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10727: Output = Z  Instr=B14 RESET T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [1, '0x11101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0x00011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10728: Output = NZ  Instr=B15 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [1, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10729: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10730: Output = NZ  Instr=B12 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0000011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10731: Output = Z  Instr=B13 READ T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10732: Output = NZ  Instr=B14 SET T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [2, '00x1101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '00x0011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10733: Output = NZ  Instr=B15 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [2, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10734: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10735: Output = NZ  Instr=B12 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0010011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10736: Output = Z  Instr=B13 READ T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10737: Output = NZ  Instr=B14 SET T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [3, '001x101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '001x011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10738: Output = NZ  Instr=B15 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [3, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10739: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10740: Output = NZ  Instr=B12 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011011100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10741: Output = Z  Instr=B13 READ T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10742: Output = NZ  Instr=B14 SET T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011x01100000000000'], 'T3': [4, '0011x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011x11100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10743: Output = NZ  Instr=B15 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [4, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10744: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10745: Output = NZ  Instr=B12 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011111100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10746: Output = NZ  Instr=B13 READ T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10747: Output = Z  Instr=B14 RESET T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [5, '00111x1100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10748: Output = NZ  Instr=B15 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10749: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10750: Output = NZ  Instr=B12 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10751: Output = NZ  Instr=B13 READ T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10752: Output = NZ  Instr=B14 SET T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [6, '001110x100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10753: Output = NZ  Instr=B15 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10754: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10755: Output = NZ  Instr=B12 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10756: Output = NZ  Instr=B13 READ T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10757: Output = NZ  Instr=B14 SET T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101x00000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10758: Output = NZ  Instr=B15 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10759: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10760: Output = NZ  Instr=B12 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10761: Output = Z  Instr=B13 READ T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10762: Output = Z  Instr=B14 RESET T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [8, '00111011x0000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10763: Output = NZ  Instr=B15 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10764: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10765: Output = NZ  Instr=B12 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10766: Output = Z  Instr=B13 READ T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10767: Output = Z  Instr=B14 RESET T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [9, '001110110x000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10768: Output = NZ  Instr=B15 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10769: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10770: Output = NZ  Instr=B12 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10771: Output = Z  Instr=B13 READ T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10772: Output = Z  Instr=B14 RESET T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100x00000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10773: Output = NZ  Instr=B15 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10774: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10775: Output = NZ  Instr=B12 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10776: Output = Z  Instr=B13 READ T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10777: Output = Z  Instr=B14 RESET T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [11, '00111011000x0000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10778: Output = NZ  Instr=B15 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10779: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10780: Output = NZ  Instr=B12 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10781: Output = Z  Instr=B13 READ T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10782: Output = Z  Instr=B14 RESET T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [12, '001110110000x000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10783: Output = NZ  Instr=B15 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10784: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10785: Output = NZ  Instr=B12 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10786: Output = Z  Instr=B13 READ T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10787: Output = Z  Instr=B14 RESET T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000x00000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10788: Output = NZ  Instr=B15 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10789: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10790: Output = NZ  Instr=B12 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10791: Output = Z  Instr=B13 READ T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10792: Output = Z  Instr=B14 RESET T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [14, '00111011000000x0000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10793: Output = NZ  Instr=B15 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10794: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10795: Output = NZ  Instr=B12 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10796: Output = Z  Instr=B13 READ T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10797: Output = Z  Instr=B14 RESET T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [15, '001110110000000x000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10798: Output = NZ  Instr=B15 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10799: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10800: Output = NZ  Instr=B12 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10801: Output = Z  Instr=B13 READ T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10802: Output = Z  Instr=B14 RESET T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000x00'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10803: Output = NZ  Instr=B15 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10804: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10805: Output = NZ  Instr=B12 READ T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10806: Output = Z  Instr=B13 READ T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10807: Output = Z  Instr=B14 RESET T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [17, '00111011000000000x0'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10808: Output = NZ  Instr=B15 INC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10809: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10810: Output = Z  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10811: Output = NZ  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10812: Output = NZ  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10813: Output = NZ  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10814: Output = NZ  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10815: Output = NZ  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10816: Output = NZ  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10817: Output = NZ  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10818: Output = NZ  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10819: Output = NZ  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10820: Output = NZ  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10821: Output = NZ  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10822: Output = NZ  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10823: Output = NZ  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10824: Output = NZ  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10825: Output = NZ  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10826: Output = NZ  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10827: Output = NZ  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10828: Output = NZ  Instr=B16 DEC T2; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10829: Output = Z  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10830: Output = NZ  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10831: Output = NZ  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10832: Output = NZ  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10833: Output = NZ  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10834: Output = NZ  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10835: Output = NZ  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10836: Output = NZ  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10837: Output = NZ  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10838: Output = NZ  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10839: Output = NZ  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10840: Output = NZ  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10841: Output = NZ  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10842: Output = NZ  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10843: Output = NZ  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10844: Output = NZ  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10845: Output = NZ  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10846: Output = NZ  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10847: Output = NZ  Instr=B17 DEC T3; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10848: Output = Z  Instr=ADD NOP; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10849: Output = Z  Instr=C1 TDEC R4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10850: Output = NZ  Instr=C2 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10851: Output = Z  Instr=C4 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10852: Output = Z  Instr=C1 TDEC R4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10853: Output = NZ  Instr=C2 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10854: Output = NZ  Instr=C3 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10855: Output = NZ  Instr=C2 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10856: Output = Z  Instr=C4 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10857: Output = NZ  Instr=C4 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10858: Output = Z  Instr=C1 TDEC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10859: Output = NZ  Instr=C2 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10860: Output = Z  Instr=C4 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10861: Output = Z  Instr=C1 TDEC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10862: Output = Z  Instr=C5 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10863: Output = Z  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10864: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10865: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10866: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10867: Output = Z  Instr=C7 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 3, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10868: Output = NZ  Instr=C7 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10869: Output = NZ  Instr=C7 INC R3; regs={'R4': 1, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 1, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10870: Output = NZ  Instr=C7 INC R3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10871: Output = Z  Instr=MUL NOP; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10872: Output = Z  Instr=D1 TDEC R4; regs={'R4': 3, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10873: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10874: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10875: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10876: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10877: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10878: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10879: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10880: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10881: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10882: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10883: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10884: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10885: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10886: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10887: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10888: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10889: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10890: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10891: Output = NZ  Instr=D2 INC R1; regs={'R4': 2, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 2, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10892: Output = Z  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10893: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10894: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10895: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10896: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10897: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10898: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10899: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10900: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10901: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10902: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10903: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10904: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10905: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10906: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10907: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10908: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10909: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10910: Output = NZ  Instr=D3 INC R0; regs={'R4': 2, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10911: Output = Z  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10912: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10913: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10914: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, 'x000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10915: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, 'x000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10916: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10917: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10918: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10919: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10920: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '1x00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10921: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '1x00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10922: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [2, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10923: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [2, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10924: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10925: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '11x1101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '1100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10926: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '11x0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10927: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '11x0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '1110000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10928: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [3, '1110000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10929: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [3, '1110000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10930: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '1110000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10931: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '1110000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '111x101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '1110000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '1110000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10932: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '111x000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10933: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '111x000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '1111000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10934: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [4, '1111000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10935: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [4, '1111000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10936: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '1111000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10937: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '1111000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111x01100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '1111000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '1111000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10938: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '1111x00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10939: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '1111x00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '1111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10940: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [5, '1111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10941: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [5, '1111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10942: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '1111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10943: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '1111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '11111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '1111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10944: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '11111x0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10945: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '11111x0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '1111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10946: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [6, '1111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10947: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [6, '1111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10948: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '1111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10949: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '1111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '111110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '1111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '1111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10950: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '111110x000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10951: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '111110x000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '1111101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10952: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [7, '1111101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10953: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [7, '1111101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10954: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '1111101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10955: Output = NZ  Instr=D6 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '1111101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '1111101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '1111101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10956: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '1111101x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
10957: Output = NZ  Instr=D8 SET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '1111101x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10958: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [8, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10959: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [8, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10960: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10961: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '11111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10962: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '11111011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10963: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '11111011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10964: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [9, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10965: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [9, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10966: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10967: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '111110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10968: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '111110110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10969: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '111110110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10970: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [10, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10971: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [10, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10972: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10973: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10974: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '1111101100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10975: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '1111101100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10976: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [11, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10977: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [11, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10978: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10979: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '11111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10980: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '11111011000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10981: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '11111011000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10982: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [12, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10983: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [12, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10984: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10985: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '111110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10986: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '111110110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10987: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '111110110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10988: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [13, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10989: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [13, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10990: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10991: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10992: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '1111101100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10993: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '1111101100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10994: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [14, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10995: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [14, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10996: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10997: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '11111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10998: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '11111011000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
10999: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '11111011000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11000: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [15, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11001: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [15, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11002: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11003: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '111110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11004: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '111110110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11005: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '111110110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11006: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [16, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11007: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [16, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11008: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11009: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11010: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '1111101100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11011: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '1111101100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11012: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [17, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11013: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [17, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11014: Output = NZ  Instr=D5 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11015: Output = Z  Instr=D6 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '11111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11016: Output = Z  Instr=D7 ADD B1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '11111011000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11017: Output = Z  Instr=D8 RESET T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '11111011000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11018: Output = NZ  Instr=D8A INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11019: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11020: Output = Z  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11021: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11022: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11023: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11024: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11025: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11026: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11027: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11028: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11029: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11030: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11031: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11032: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11033: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11034: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11035: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11036: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11037: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11038: Output = NZ  Instr=D9 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11039: Output = Z  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11040: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11041: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [16, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11042: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [15, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11043: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [14, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11044: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [13, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11045: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [12, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11046: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [11, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11047: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [10, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11048: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11049: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [8, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11050: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [7, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11051: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [6, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11052: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [5, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11053: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [4, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11054: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [3, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11055: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [2, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11056: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [1, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11057: Output = NZ  Instr=D10 DEC T4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11058: Output = Z  Instr=D1 TDEC R4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11059: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11060: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11061: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11062: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11063: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11064: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11065: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11066: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11067: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11068: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11069: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11070: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11071: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11072: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11073: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11074: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11075: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11076: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11077: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11078: Output = Z  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11079: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11080: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11081: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11082: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11083: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11084: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11085: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11086: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11087: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11088: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11089: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11090: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11091: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11092: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11093: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11094: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11095: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11096: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11097: Output = Z  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11098: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11099: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '1111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11100: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, 'x111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11101: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, 'x111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11102: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [1, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11103: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [1, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11104: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11105: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11106: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '0x11101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11107: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '0x11101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11108: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [2, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11109: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [2, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11110: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11111: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '11x1101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11112: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '01x1101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11113: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '01x1101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11114: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [3, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11115: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [3, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11116: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11117: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '111x101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11118: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '011x101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11119: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '011x101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11120: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [4, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11121: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [4, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11122: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11123: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111x01100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11124: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '0111x01100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11125: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '0111x01100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11126: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [5, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11127: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [5, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11128: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11129: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '11111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11130: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '01111x1100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11131: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '01111x1100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '0111111100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11132: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [6, '0111111100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11133: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [6, '0111111100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11134: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '0111111100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11135: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '0111111100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '111110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '0111111100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '0111111100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11136: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '011111x100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11137: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '011111x100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '0111110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11138: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [7, '0111110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11139: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [7, '0111110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11140: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '0111110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11141: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '0111110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '0111110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '0111110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11142: Output = NZ  Instr=D7 ADD B0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '0111110x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11143: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '0111110x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '0111110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11144: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [8, '0111110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11145: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [8, '0111110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11146: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '0111110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11147: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '0111110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '11111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '0111110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11148: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '01111101x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11149: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '01111101x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11150: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [9, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11151: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [9, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11152: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11153: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '111110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11154: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '011111011x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11155: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '011111011x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11156: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [10, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11157: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [10, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11158: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11159: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11160: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '0111110110x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11161: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '0111110110x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11162: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [11, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11163: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [11, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11164: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11165: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '11111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11166: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '01111101100x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11167: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '01111101100x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11168: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [12, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11169: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [12, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11170: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11171: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '111110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11172: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '011111011000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11173: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '011111011000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11174: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [13, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11175: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [13, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11176: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11177: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11178: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '0111110110000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11179: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '0111110110000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11180: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [14, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11181: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [14, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11182: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11183: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '11111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11184: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '01111101100000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11185: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '01111101100000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11186: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [15, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11187: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [15, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11188: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11189: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '111110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11190: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '011111011000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11191: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '011111011000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11192: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [16, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11193: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [16, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11194: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11195: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11196: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '0111110110000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11197: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '0111110110000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11198: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [17, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11199: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [17, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11200: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11201: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '11111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11202: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '01111101100000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11203: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '01111101100000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11204: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11205: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11206: Output = Z  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11207: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11208: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11209: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11210: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11211: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11212: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11213: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11214: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11215: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11216: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11217: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11218: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11219: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11220: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11221: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11222: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11223: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11224: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11225: Output = Z  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11226: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11227: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [16, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11228: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [15, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11229: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [14, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11230: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [13, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11231: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [12, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11232: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [11, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11233: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [10, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11234: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11235: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [8, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11236: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [7, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11237: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [6, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11238: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [5, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11239: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [4, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11240: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [3, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11241: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [2, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11242: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [1, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11243: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11244: Output = Z  Instr=D1 TDEC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11245: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11246: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11247: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11248: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11249: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11250: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11251: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11252: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11253: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11254: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11255: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11256: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11257: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11258: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11259: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11260: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11261: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11262: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11263: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11264: Output = Z  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11265: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11266: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11267: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11268: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11269: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11270: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11271: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11272: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11273: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11274: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11275: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11276: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11277: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11278: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11279: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11280: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11281: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11282: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11283: Output = Z  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11284: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11285: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '0111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11286: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, 'x111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11287: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, 'x111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '1111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11288: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [1, '1111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11289: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [1, '1111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11290: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '1111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11291: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '1111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '1111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '1111110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11292: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '1x11110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11293: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '1x11110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11294: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [2, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11295: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [2, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11296: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11297: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '11x1101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11298: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '10x1110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11299: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '10x1110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11300: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [3, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11301: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [3, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11302: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11303: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '111x101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11304: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '101x110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11305: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '101x110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11306: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [4, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11307: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [4, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11308: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11309: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111x01100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11310: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '1011x10110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11311: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '1011x10110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11312: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [5, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11313: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [5, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11314: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11315: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '11111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '1011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11316: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '10111x0110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11317: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '10111x0110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11318: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [6, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11319: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [6, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11320: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11321: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '111110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11322: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '101110x110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11323: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '101110x110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11324: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [7, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11325: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [7, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11326: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11327: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11328: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '1011100x10000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
11329: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '1011100x10000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11330: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [8, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11331: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [8, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11332: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11333: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '11111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '1011100110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11334: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '10111001x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11335: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '10111001x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '1011100100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11336: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [9, '1011100100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11337: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [9, '1011100100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11338: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '1011100100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11339: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '1011100100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '111110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '1011100100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11340: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '101110010x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
11341: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '101110010x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11342: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [10, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11343: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [10, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11344: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11345: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11346: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '1011100101x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11347: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '1011100101x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11348: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [11, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11349: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [11, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11350: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11351: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '11111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11352: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '10111001010x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11353: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '10111001010x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11354: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [12, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11355: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [12, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11356: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11357: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '111110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11358: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '101110010100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11359: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '101110010100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11360: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [13, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11361: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [13, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11362: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11363: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11364: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '1011100101000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11365: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '1011100101000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11366: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [14, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11367: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [14, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11368: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11369: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '11111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11370: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '10111001010000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11371: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '10111001010000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11372: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [15, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11373: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [15, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11374: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11375: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '111110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11376: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '101110010100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11377: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '101110010100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11378: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [16, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11379: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [16, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11380: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11381: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11382: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '1011100101000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11383: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '1011100101000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11384: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [17, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11385: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [17, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11386: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11387: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '11111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11388: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '10111001010000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11389: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '10111001010000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11390: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11391: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11392: Output = Z  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11393: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11394: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11395: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11396: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11397: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11398: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11399: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11400: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11401: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11402: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11403: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11404: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11405: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11406: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11407: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11408: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11409: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11410: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11411: Output = Z  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11412: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11413: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [16, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11414: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [15, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11415: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [14, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11416: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [13, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11417: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [12, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11418: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [11, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11419: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [10, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11420: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11421: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [8, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11422: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [7, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11423: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [6, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11424: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [5, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11425: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [4, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11426: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [3, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11427: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [2, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11428: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [1, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11429: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11430: Output = Z  Instr=D1 TDEC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11431: Output = Z  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11432: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11433: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11434: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11435: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11436: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11437: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11438: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11439: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11440: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11441: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11442: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11443: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11444: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11445: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11446: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11447: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11448: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11449: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11450: Output = Z  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11451: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11452: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11453: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11454: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11455: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11456: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11457: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11458: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11459: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11460: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11461: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11462: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11463: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11464: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11465: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11466: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11467: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11468: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11469: Output = Z  Instr=COMP NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11470: Output = Z  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11471: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11472: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11473: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 3, 'T4': [1, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11474: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11475: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [1, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11476: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 3, 'T4': [2, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11477: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11478: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [2, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11479: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 3, 'T4': [3, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11480: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11481: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [3, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11482: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 3, 'T4': [4, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11483: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11484: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [4, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11485: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 3, 'T4': [5, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11486: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11487: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [5, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11488: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 3, 'T4': [6, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11489: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11490: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [6, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11491: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 3, 'T4': [7, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11492: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11493: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [7, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11494: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 3, 'T4': [8, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11495: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11496: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [8, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11497: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11498: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11499: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11500: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 3, 'T4': [10, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11501: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11502: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [10, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11503: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 3, 'T4': [11, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11504: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11505: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [11, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11506: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 3, 'T4': [12, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11507: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11508: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [12, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11509: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 3, 'T4': [13, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11510: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11511: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [13, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11512: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 3, 'T4': [14, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11513: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11514: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [14, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11515: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 3, 'T4': [15, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11516: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11517: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [15, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11518: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 3, 'T4': [16, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11519: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11520: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [16, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11521: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 3, 'T4': [17, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11522: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11523: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11524: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11525: Output = Z  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11526: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '000010011000000000x'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11527: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '101110010100000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [18, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11528: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11529: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11530: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '00001001100000000x0'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11531: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '10111001010000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [17, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11532: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [16, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11533: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [16, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11534: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [16, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000x00'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [16, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11535: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [16, '1011100101000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [16, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11536: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [15, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11537: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [15, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11538: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [15, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '000010011000000x000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [15, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11539: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [15, '101110010100000x000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [15, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11540: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [14, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11541: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [14, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11542: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [14, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '00001001100000x0000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [14, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11543: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [14, '10111001010000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [14, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11544: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [13, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11545: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [13, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11546: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [13, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000x00000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [13, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11547: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [13, '1011100101000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [13, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11548: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [12, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11549: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [12, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11550: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [12, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '000010011000x000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [12, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11551: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [12, '101110010100x000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [12, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11552: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [11, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11553: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [11, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11554: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [11, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '00001001100x0000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [11, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11555: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [11, '10111001010x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [11, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11556: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [10, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11557: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [10, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11558: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [10, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110x00000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [10, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11559: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [10, '1011100101x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [10, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11560: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11561: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11562: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '000010011x000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11563: Output = NZ  Instr=E9 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '101110010x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11564: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11565: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11566: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11567: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11568: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11569: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11570: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11571: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11572: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11573: Output = Z  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [9, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11574: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [8, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11575: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [7, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11576: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [6, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11577: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [5, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11578: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [4, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11579: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [3, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11580: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [2, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11581: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [1, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11582: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11583: Output = Z  Instr=E11 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 3, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11584: Output = NZ  Instr=EVL NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11585: Output = Z  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11586: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11587: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11588: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11589: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11590: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11591: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11592: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11593: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11594: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11595: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11596: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11597: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11598: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11599: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11600: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11601: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11602: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11603: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11604: Output = Z  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11605: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11606: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11607: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11608: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11609: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11610: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11611: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11612: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11613: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11614: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11615: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11616: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11617: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11618: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11619: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11620: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11621: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11622: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11623: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11624: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '1011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11625: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, 'x011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11626: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [1, '0011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11627: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11628: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0x11100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11629: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [2, '0011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11630: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '0011100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11631: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '00x1100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '0001100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11632: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [3, '0001100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11633: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '0001100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11634: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '000x100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11635: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [4, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11636: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0000100101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11637: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0000x00101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11638: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [5, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11639: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [5, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11640: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [5, '00000x0101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [5, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11641: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [6, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11642: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11643: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '000000x101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11644: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [7, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11645: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0000000101000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11646: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0000000x01000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0000000001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11647: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [8, '0000000001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11648: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [8, '0000000001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11649: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [8, '00000000x1000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [8, '0000000001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11650: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [9, '0000000001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11651: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [9, '0000000001000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11652: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [9, '000000000x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [9, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11653: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11654: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11655: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [10, '0000000000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11656: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11657: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11658: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [11, '00000000000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11659: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11660: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11661: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [12, '000000000000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11662: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11663: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11664: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [13, '0000000000000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11665: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11666: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11667: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [14, '00000000000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11668: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11669: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11670: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [15, '000000000000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11671: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11672: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11673: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [16, '0000000000000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11674: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11675: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11676: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '00000000000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11677: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11678: Output = Z  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11679: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11680: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11681: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11682: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11683: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11684: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11685: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11686: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11687: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [9, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11688: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [8, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11689: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [7, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11690: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [6, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11691: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [5, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11692: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [4, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11693: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [3, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11694: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11695: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11696: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11697: Output = Z  Instr=B5 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11698: Output = Z  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11699: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11700: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11701: Output = Z  Instr=B7 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11702: Output = NZ  Instr=B7 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11703: Output = NZ  Instr=B7 INC R3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11704: Output = Z  Instr=B8 NOP; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11705: Output = Z  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11706: Output = NZ  Instr=B9 INC R1; regs={'R4': 2, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11707: Output = NZ  Instr=B9 INC R1; regs={'R4': 2, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11708: Output = NZ  Instr=B9 INC R1; regs={'R4': 2, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11709: Output = NZ  Instr=B9 INC R1; regs={'R4': 2, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11710: Output = NZ  Instr=B9 INC R1; regs={'R4': 2, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11711: Output = NZ  Instr=B9 INC R1; regs={'R4': 2, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11712: Output = NZ  Instr=B9 INC R1; regs={'R4': 2, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11713: Output = NZ  Instr=B9 INC R1; regs={'R4': 2, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11714: Output = NZ  Instr=B9 INC R1; regs={'R4': 2, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11715: Output = NZ  Instr=B9 INC R1; regs={'R4': 2, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11716: Output = NZ  Instr=B9 INC R1; regs={'R4': 2, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11717: Output = NZ  Instr=B9 INC R1; regs={'R4': 2, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11718: Output = NZ  Instr=B9 INC R1; regs={'R4': 2, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11719: Output = NZ  Instr=B9 INC R1; regs={'R4': 2, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11720: Output = NZ  Instr=B9 INC R1; regs={'R4': 2, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11721: Output = NZ  Instr=B9 INC R1; regs={'R4': 2, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11722: Output = NZ  Instr=B9 INC R1; regs={'R4': 2, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11723: Output = NZ  Instr=B9 INC R1; regs={'R4': 2, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 2, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11724: Output = Z  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11725: Output = NZ  Instr=B10 INC R0; regs={'R4': 2, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11726: Output = NZ  Instr=B10 INC R0; regs={'R4': 2, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11727: Output = NZ  Instr=B10 INC R0; regs={'R4': 2, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11728: Output = NZ  Instr=B10 INC R0; regs={'R4': 2, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11729: Output = NZ  Instr=B10 INC R0; regs={'R4': 2, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11730: Output = NZ  Instr=B10 INC R0; regs={'R4': 2, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11731: Output = NZ  Instr=B10 INC R0; regs={'R4': 2, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11732: Output = NZ  Instr=B10 INC R0; regs={'R4': 2, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11733: Output = NZ  Instr=B10 INC R0; regs={'R4': 2, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11734: Output = NZ  Instr=B10 INC R0; regs={'R4': 2, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11735: Output = NZ  Instr=B10 INC R0; regs={'R4': 2, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11736: Output = NZ  Instr=B10 INC R0; regs={'R4': 2, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11737: Output = NZ  Instr=B10 INC R0; regs={'R4': 2, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11738: Output = NZ  Instr=B10 INC R0; regs={'R4': 2, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11739: Output = NZ  Instr=B10 INC R0; regs={'R4': 2, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11740: Output = NZ  Instr=B10 INC R0; regs={'R4': 2, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11741: Output = NZ  Instr=B10 INC R0; regs={'R4': 2, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11742: Output = NZ  Instr=B10 INC R0; regs={'R4': 2, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11743: Output = Z  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11744: Output = NZ  Instr=B12 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11745: Output = NZ  Instr=B13 READ T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11746: Output = Z  Instr=B14 RESET T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, 'x011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11747: Output = NZ  Instr=B15 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11748: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11749: Output = NZ  Instr=B12 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11750: Output = NZ  Instr=B13 READ T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11751: Output = Z  Instr=B14 RESET T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [1, '0x11101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11752: Output = NZ  Instr=B15 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11753: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11754: Output = NZ  Instr=B12 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11755: Output = NZ  Instr=B13 READ T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '00x1101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11756: Output = NZ  Instr=B14 SET T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [2, '00x1101100000000000'], 'T3': [2, '00x1101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '00x1101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11757: Output = NZ  Instr=B15 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11758: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11759: Output = NZ  Instr=B12 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11760: Output = NZ  Instr=B13 READ T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '001x101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11761: Output = NZ  Instr=B14 SET T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [3, '001x101100000000000'], 'T3': [3, '001x101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '001x101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11762: Output = NZ  Instr=B15 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [3, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11763: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11764: Output = NZ  Instr=B12 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11765: Output = NZ  Instr=B13 READ T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011x01100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11766: Output = NZ  Instr=B14 SET T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011x01100000000000'], 'T3': [4, '0011x01100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011x01100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11767: Output = NZ  Instr=B15 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [4, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11768: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11769: Output = NZ  Instr=B12 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11770: Output = Z  Instr=B13 READ T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11771: Output = Z  Instr=B14 RESET T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [5, '00111x1100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11772: Output = NZ  Instr=B15 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11773: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11774: Output = NZ  Instr=B12 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11775: Output = NZ  Instr=B13 READ T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11776: Output = NZ  Instr=B14 SET T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [6, '001110x100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11777: Output = NZ  Instr=B15 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11778: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11779: Output = NZ  Instr=B12 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11780: Output = NZ  Instr=B13 READ T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11781: Output = NZ  Instr=B14 SET T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101x00000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11782: Output = NZ  Instr=B15 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11783: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11784: Output = NZ  Instr=B12 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11785: Output = Z  Instr=B13 READ T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11786: Output = Z  Instr=B14 RESET T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [8, '00111011x0000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11787: Output = NZ  Instr=B15 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11788: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11789: Output = NZ  Instr=B12 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11790: Output = Z  Instr=B13 READ T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11791: Output = Z  Instr=B14 RESET T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [9, '001110110x000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11792: Output = NZ  Instr=B15 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11793: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11794: Output = NZ  Instr=B12 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11795: Output = Z  Instr=B13 READ T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11796: Output = Z  Instr=B14 RESET T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100x00000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11797: Output = NZ  Instr=B15 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11798: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11799: Output = NZ  Instr=B12 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11800: Output = Z  Instr=B13 READ T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11801: Output = Z  Instr=B14 RESET T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [11, '00111011000x0000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11802: Output = NZ  Instr=B15 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11803: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11804: Output = NZ  Instr=B12 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11805: Output = Z  Instr=B13 READ T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11806: Output = Z  Instr=B14 RESET T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [12, '001110110000x000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11807: Output = NZ  Instr=B15 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11808: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11809: Output = NZ  Instr=B12 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11810: Output = Z  Instr=B13 READ T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11811: Output = Z  Instr=B14 RESET T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000x00000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11812: Output = NZ  Instr=B15 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11813: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11814: Output = NZ  Instr=B12 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11815: Output = Z  Instr=B13 READ T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11816: Output = Z  Instr=B14 RESET T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [14, '00111011000000x0000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11817: Output = NZ  Instr=B15 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11818: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11819: Output = NZ  Instr=B12 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11820: Output = Z  Instr=B13 READ T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11821: Output = Z  Instr=B14 RESET T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [15, '001110110000000x000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11822: Output = NZ  Instr=B15 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11823: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11824: Output = NZ  Instr=B12 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11825: Output = Z  Instr=B13 READ T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11826: Output = Z  Instr=B14 RESET T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000x00'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11827: Output = NZ  Instr=B15 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11828: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11829: Output = NZ  Instr=B12 READ T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11830: Output = Z  Instr=B13 READ T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11831: Output = Z  Instr=B14 RESET T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [17, '00111011000000000x0'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11832: Output = NZ  Instr=B15 INC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11833: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11834: Output = Z  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11835: Output = NZ  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11836: Output = NZ  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11837: Output = NZ  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11838: Output = NZ  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11839: Output = NZ  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11840: Output = NZ  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11841: Output = NZ  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11842: Output = NZ  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11843: Output = NZ  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11844: Output = NZ  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11845: Output = NZ  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11846: Output = NZ  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11847: Output = NZ  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11848: Output = NZ  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11849: Output = NZ  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11850: Output = NZ  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11851: Output = NZ  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11852: Output = NZ  Instr=B16 DEC T2; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11853: Output = Z  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11854: Output = NZ  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11855: Output = NZ  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11856: Output = NZ  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11857: Output = NZ  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11858: Output = NZ  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11859: Output = NZ  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11860: Output = NZ  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11861: Output = NZ  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11862: Output = NZ  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11863: Output = NZ  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11864: Output = NZ  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11865: Output = NZ  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11866: Output = NZ  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11867: Output = NZ  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11868: Output = NZ  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11869: Output = NZ  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11870: Output = NZ  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11871: Output = NZ  Instr=B17 DEC T3; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11872: Output = Z  Instr=ADD NOP; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11873: Output = Z  Instr=C1 TDEC R4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11874: Output = NZ  Instr=C2 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11875: Output = Z  Instr=C4 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11876: Output = Z  Instr=C1 TDEC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11877: Output = NZ  Instr=C2 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11878: Output = NZ  Instr=C3 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C3 INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11879: Output = NZ  Instr=C2 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11880: Output = Z  Instr=C4 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11881: Output = NZ  Instr=C4 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11882: Output = Z  Instr=C1 TDEC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11883: Output = Z  Instr=C5 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11884: Output = Z  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11885: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11886: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11887: Output = Z  Instr=C7 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 2, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11888: Output = NZ  Instr=C7 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11889: Output = NZ  Instr=C7 INC R3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11890: Output = Z  Instr=MUL NOP; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11891: Output = Z  Instr=D1 TDEC R4; regs={'R4': 2, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11892: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11893: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11894: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11895: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11896: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11897: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11898: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11899: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11900: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11901: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11902: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11903: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11904: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11905: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11906: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11907: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11908: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11909: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11910: Output = NZ  Instr=D2 INC R1; regs={'R4': 1, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 1, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11911: Output = Z  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11912: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11913: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11914: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11915: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11916: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11917: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11918: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11919: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11920: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11921: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11922: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11923: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11924: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11925: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11926: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11927: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11928: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11929: Output = NZ  Instr=D3 INC R0; regs={'R4': 1, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11930: Output = Z  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11931: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11932: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11933: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, 'x000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11934: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, 'x000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11935: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11936: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11937: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11938: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11939: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0x00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11940: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0x00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11941: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [2, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11942: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [2, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11943: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11944: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '01x1101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '0100000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11945: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '01x0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11946: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '01x0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '0110000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11947: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [3, '0110000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11948: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [3, '0110000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11949: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '0110000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11950: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '0110000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '011x101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '0110000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '0110000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11951: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '011x000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11952: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '011x000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '0111000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11953: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [4, '0111000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11954: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [4, '0111000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11955: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0111000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11956: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0111000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111x01100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0111000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0111000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11957: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0111x00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11958: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0111x00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11959: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [5, '0111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11960: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [5, '0111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11961: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [5, '0111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11962: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [5, '0111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '01111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [5, '0111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11963: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [5, '01111x0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11964: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [5, '01111x0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [5, '0111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11965: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [6, '0111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11966: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [6, '0111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11967: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '0111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11968: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '0111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '011110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '0111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '0111100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11969: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '011110x000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11970: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '011110x000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '0111101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11971: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [7, '0111101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11972: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [7, '0111101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11973: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0111101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11974: Output = NZ  Instr=D6 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0111101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0111101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0111101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11975: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0111101x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
11976: Output = NZ  Instr=D8 SET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0111101x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11977: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [8, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11978: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [8, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11979: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [8, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11980: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [8, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '01111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [8, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11981: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [8, '01111011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11982: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [8, '01111011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [8, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11983: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [9, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11984: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [9, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11985: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [9, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11986: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [9, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '011110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [9, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11987: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [9, '011110110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11988: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [9, '011110110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [9, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11989: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [10, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11990: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [10, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11991: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [10, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11992: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [10, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0111101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [10, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11993: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [10, '0111101100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11994: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [10, '0111101100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [10, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11995: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [11, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11996: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [11, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11997: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [11, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11998: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [11, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '01111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [11, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
11999: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [11, '01111011000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12000: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [11, '01111011000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [11, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12001: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [12, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12002: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [12, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12003: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [12, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12004: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [12, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '011110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [12, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12005: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [12, '011110110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12006: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [12, '011110110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [12, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12007: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [13, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12008: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [13, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12009: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [13, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12010: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [13, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0111101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [13, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12011: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [13, '0111101100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12012: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [13, '0111101100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [13, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12013: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [14, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12014: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [14, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12015: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [14, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12016: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [14, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '01111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [14, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12017: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [14, '01111011000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12018: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [14, '01111011000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [14, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12019: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [15, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12020: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [15, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12021: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [15, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12022: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [15, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '011110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [15, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12023: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [15, '011110110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12024: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [15, '011110110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [15, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12025: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [16, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12026: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [16, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12027: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [16, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12028: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [16, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0111101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [16, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12029: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [16, '0111101100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12030: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [16, '0111101100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [16, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12031: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [17, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12032: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [17, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12033: Output = NZ  Instr=D5 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12034: Output = Z  Instr=D6 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '01111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12035: Output = Z  Instr=D7 ADD B1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '01111011000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12036: Output = Z  Instr=D8 RESET T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '01111011000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12037: Output = NZ  Instr=D8A INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12038: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12039: Output = Z  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12040: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12041: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12042: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12043: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12044: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12045: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12046: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12047: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12048: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12049: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12050: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12051: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12052: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12053: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12054: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12055: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12056: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12057: Output = NZ  Instr=D9 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12058: Output = Z  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12059: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12060: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [16, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12061: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [15, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12062: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [14, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12063: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [13, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12064: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [12, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12065: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [11, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12066: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [10, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12067: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [9, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12068: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [8, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12069: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [7, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12070: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [6, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12071: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [5, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12072: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [4, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12073: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [3, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12074: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [2, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12075: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [1, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12076: Output = NZ  Instr=D10 DEC T4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12077: Output = Z  Instr=D1 TDEC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12078: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12079: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12080: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12081: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12082: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12083: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12084: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12085: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12086: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12087: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12088: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12089: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12090: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12091: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12092: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12093: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12094: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12095: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12096: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12097: Output = Z  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12098: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12099: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12100: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12101: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12102: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12103: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12104: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12105: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12106: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12107: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12108: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12109: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12110: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12111: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12112: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12113: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12114: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12115: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12116: Output = Z  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12117: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12118: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12119: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, 'x111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12120: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, 'x111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12121: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [1, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12122: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [1, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12123: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12124: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0111101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
12125: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0x11101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
12126: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0x11101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12127: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [2, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12128: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [2, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12129: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12130: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '01x1101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
12131: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '00x1101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
12132: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '00x1101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12133: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [3, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12134: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [3, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12135: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12136: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '011x101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
12137: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '001x101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
12138: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '001x101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12139: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [4, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12140: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [4, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12141: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12142: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111x01100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
12143: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0011x01100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
12144: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0011x01100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12145: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [5, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12146: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [5, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12147: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [5, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12148: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [5, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '01111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [5, '0011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12149: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [5, '00111x1100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12150: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [5, '00111x1100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [5, '0011111100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12151: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [6, '0011111100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12152: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [6, '0011111100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12153: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '0011111100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12154: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '0011111100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '011110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '0011111100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '0011111100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
12155: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '001111x100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
12156: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '001111x100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '0011110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12157: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [7, '0011110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12158: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [7, '0011110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12159: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0011110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12160: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0011110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0011110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0011110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
12161: Output = NZ  Instr=D7 ADD B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0011110x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '110 bit0', 'MUL': '00000'}; mem={}
12162: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0011110x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0011110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12163: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [8, '0011110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12164: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [8, '0011110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12165: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [8, '0011110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12166: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [8, '0011110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '01111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [8, '0011110100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12167: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [8, '00111101x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '100 bit1', 'MUL': '00000'}; mem={}
12168: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [8, '00111101x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [8, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12169: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [9, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12170: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [9, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12171: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [9, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12172: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [9, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '011110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [9, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12173: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [9, '001111011x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12174: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [9, '001111011x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [9, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12175: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [10, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12176: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [10, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12177: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [10, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12178: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [10, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0111101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [10, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12179: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [10, '0011110110x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12180: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [10, '0011110110x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [10, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12181: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [11, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12182: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [11, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12183: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [11, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12184: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [11, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '01111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [11, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12185: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [11, '00111101100x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12186: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [11, '00111101100x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [11, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12187: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [12, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12188: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [12, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12189: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [12, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12190: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [12, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '011110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [12, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12191: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [12, '001111011000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12192: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [12, '001111011000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [12, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12193: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [13, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12194: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [13, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12195: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [13, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12196: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [13, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0111101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [13, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12197: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [13, '0011110110000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12198: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [13, '0011110110000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [13, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12199: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [14, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12200: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [14, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12201: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [14, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12202: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [14, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '01111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [14, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12203: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [14, '00111101100000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12204: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [14, '00111101100000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [14, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12205: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [15, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12206: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [15, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12207: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [15, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12208: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [15, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '011110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [15, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12209: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [15, '001111011000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12210: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [15, '001111011000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [15, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12211: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [16, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12212: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [16, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12213: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [16, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12214: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [16, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0111101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [16, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12215: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [16, '0011110110000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12216: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [16, '0011110110000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [16, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12217: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [17, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12218: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [17, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12219: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12220: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '01111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12221: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '00111101100000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12222: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '00111101100000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12223: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12224: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12225: Output = Z  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12226: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12227: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12228: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12229: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12230: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12231: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12232: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12233: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12234: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12235: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12236: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12237: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12238: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12239: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12240: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12241: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12242: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12243: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12244: Output = Z  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12245: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12246: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [16, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12247: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [15, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12248: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [14, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12249: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [13, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12250: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [12, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12251: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [11, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12252: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [10, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12253: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [9, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12254: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [8, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12255: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [7, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12256: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [6, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12257: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [5, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12258: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [4, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12259: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [3, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12260: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [2, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12261: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [1, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12262: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12263: Output = Z  Instr=D1 TDEC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12264: Output = Z  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12265: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12266: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12267: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12268: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12269: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12270: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12271: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12272: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12273: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12274: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12275: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12276: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12277: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12278: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12279: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12280: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12281: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12282: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12283: Output = Z  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12284: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12285: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12286: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12287: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12288: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12289: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12290: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12291: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12292: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12293: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12294: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12295: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12296: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12297: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12298: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12299: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12300: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12301: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12302: Output = Z  Instr=COMP NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12303: Output = Z  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12304: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12305: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12306: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 2, 'T4': [1, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12307: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12308: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [1, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12309: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 2, 'T4': [2, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12310: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12311: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [2, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12312: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 2, 'T4': [3, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12313: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12314: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [3, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12315: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 2, 'T4': [4, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12316: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12317: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [4, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12318: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 2, 'T4': [5, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12319: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [5, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12320: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [5, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12321: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 2, 'T4': [6, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12322: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12323: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [6, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12324: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 2, 'T4': [7, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12325: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12326: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [7, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12327: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 2, 'T4': [8, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12328: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [8, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12329: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [8, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12330: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 2, 'T4': [9, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12331: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [9, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12332: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [9, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12333: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 2, 'T4': [10, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12334: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [10, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12335: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [10, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12336: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 2, 'T4': [11, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12337: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [11, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12338: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [11, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12339: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 2, 'T4': [12, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12340: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [12, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12341: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [12, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12342: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 2, 'T4': [13, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12343: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [13, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12344: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [13, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12345: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 2, 'T4': [14, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12346: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [14, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12347: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [14, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12348: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 2, 'T4': [15, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12349: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [15, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12350: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [15, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12351: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 2, 'T4': [16, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12352: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [16, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12353: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [16, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12354: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 2, 'T4': [17, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12355: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12356: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12357: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12358: Output = Z  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12359: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '000010011000000000x'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12360: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '001111011000000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [18, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12361: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12362: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12363: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '00001001100000000x0'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12364: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '00111101100000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [17, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12365: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [16, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12366: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [16, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12367: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [16, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000x00'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [16, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12368: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [16, '0011110110000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [16, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12369: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [15, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12370: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [15, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12371: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [15, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '000010011000000x000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [15, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12372: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [15, '001111011000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [15, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12373: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [14, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12374: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [14, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12375: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [14, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '00001001100000x0000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [14, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12376: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [14, '00111101100000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [14, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12377: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [13, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12378: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [13, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12379: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [13, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000x00000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [13, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12380: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [13, '0011110110000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [13, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12381: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [12, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12382: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [12, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12383: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [12, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '000010011000x000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [12, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12384: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [12, '001111011000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [12, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12385: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [11, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12386: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [11, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12387: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [11, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '00001001100x0000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [11, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12388: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [11, '00111101100x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [11, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12389: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [10, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12390: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [10, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12391: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [10, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110x00000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [10, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12392: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [10, '0011110110x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [10, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12393: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [9, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12394: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [9, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12395: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [9, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '000010011x000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [9, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12396: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [9, '001111011x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [9, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12397: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [8, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12398: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [8, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12399: Output = NZ  Instr=E8 SET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [8, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '00001001x0000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E8 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [8, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12400: Output = NZ  Instr=E6 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [8, '00111101x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [8, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12401: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [7, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12402: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [7, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12403: Output = NZ  Instr=E8 SET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [7, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100x10000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E8 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [7, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12404: Output = NZ  Instr=E6 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [7, '0011110x10000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [7, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12405: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [6, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12406: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [6, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12407: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [6, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '000010x110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [6, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12408: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [6, '001111x110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [6, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12409: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [5, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12410: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [5, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12411: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [5, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '00001x0110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [5, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12412: Output = NZ  Instr=E9 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [5, '00111x0110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [5, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12413: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [5, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12414: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [5, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12415: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [5, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12416: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [5, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12417: Output = NZ  Instr=E9 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [5, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12418: Output = Z  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [5, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12419: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [4, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12420: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [3, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12421: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [2, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12422: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [1, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12423: Output = NZ  Instr=E10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12424: Output = Z  Instr=E11 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 2, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12425: Output = NZ  Instr=EVL NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12426: Output = Z  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12427: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12428: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12429: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12430: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12431: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12432: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12433: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12434: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12435: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12436: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12437: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12438: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12439: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12440: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12441: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12442: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12443: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12444: Output = NZ  Instr=B1 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B1 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12445: Output = Z  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12446: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12447: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12448: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12449: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12450: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12451: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12452: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12453: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12454: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12455: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12456: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12457: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12458: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12459: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12460: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12461: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12462: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12463: Output = NZ  Instr=B2 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B2 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12464: Output = Z  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12465: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12466: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, 'x011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12467: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [1, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12468: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [1, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12469: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [1, '0x11110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [1, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12470: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [2, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12471: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [2, '0011110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12472: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [2, '00x1110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [2, '0001110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12473: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [3, '0001110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12474: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [3, '0001110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12475: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [3, '000x110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [3, '0000110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12476: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [4, '0000110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12477: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [4, '0000110110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12478: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [4, '0000x10110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [4, '0000010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12479: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [5, '0000010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12480: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [5, '0000010110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12481: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [5, '00000x0110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [5, '0000000110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12482: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [6, '0000000110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12483: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [6, '0000000110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12484: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [6, '000000x110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [6, '0000000110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12485: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [7, '0000000110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12486: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [7, '0000000110000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12487: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [7, '0000000x10000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [7, '0000000010000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12488: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [8, '0000000010000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12489: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [8, '0000000010000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12490: Output = NZ  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [8, '00000000x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [8, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12491: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [9, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12492: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [9, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12493: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [9, '000000000x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [9, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12494: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12495: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12496: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [10, '0000000000x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12497: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12498: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12499: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [11, '00000000000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12500: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12501: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12502: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [12, '000000000000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12503: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12504: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12505: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [13, '0000000000000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12506: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12507: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12508: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [14, '00000000000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12509: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12510: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12511: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [15, '000000000000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12512: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12513: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12514: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [16, '0000000000000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12515: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12516: Output = NZ  Instr=B4 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12517: Output = Z  Instr=B4A RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '00000000000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B4A INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12518: Output = NZ  Instr=B3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12519: Output = Z  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12520: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12521: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [16, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12522: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [15, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12523: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [14, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12524: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [13, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12525: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [12, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12526: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [11, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12527: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [10, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12528: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [9, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12529: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [8, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12530: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [7, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12531: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [6, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12532: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [5, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12533: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [4, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12534: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [3, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12535: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [2, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12536: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [1, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12537: Output = NZ  Instr=B4B DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12538: Output = Z  Instr=B5 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12539: Output = Z  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12540: Output = NZ  Instr=B6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12541: Output = Z  Instr=B7 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12542: Output = NZ  Instr=B7 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 INC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B7 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12543: Output = Z  Instr=B8 NOP; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12544: Output = Z  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12545: Output = NZ  Instr=B9 INC R1; regs={'R4': 1, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12546: Output = NZ  Instr=B9 INC R1; regs={'R4': 1, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12547: Output = NZ  Instr=B9 INC R1; regs={'R4': 1, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12548: Output = NZ  Instr=B9 INC R1; regs={'R4': 1, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12549: Output = NZ  Instr=B9 INC R1; regs={'R4': 1, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12550: Output = NZ  Instr=B9 INC R1; regs={'R4': 1, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12551: Output = NZ  Instr=B9 INC R1; regs={'R4': 1, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12552: Output = NZ  Instr=B9 INC R1; regs={'R4': 1, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12553: Output = NZ  Instr=B9 INC R1; regs={'R4': 1, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12554: Output = NZ  Instr=B9 INC R1; regs={'R4': 1, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12555: Output = NZ  Instr=B9 INC R1; regs={'R4': 1, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12556: Output = NZ  Instr=B9 INC R1; regs={'R4': 1, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12557: Output = NZ  Instr=B9 INC R1; regs={'R4': 1, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12558: Output = NZ  Instr=B9 INC R1; regs={'R4': 1, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12559: Output = NZ  Instr=B9 INC R1; regs={'R4': 1, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12560: Output = NZ  Instr=B9 INC R1; regs={'R4': 1, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12561: Output = NZ  Instr=B9 INC R1; regs={'R4': 1, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12562: Output = NZ  Instr=B9 INC R1; regs={'R4': 1, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B9 TDEC R0; regs={'R4': 1, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12563: Output = Z  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12564: Output = NZ  Instr=B10 INC R0; regs={'R4': 1, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12565: Output = NZ  Instr=B10 INC R0; regs={'R4': 1, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12566: Output = NZ  Instr=B10 INC R0; regs={'R4': 1, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12567: Output = NZ  Instr=B10 INC R0; regs={'R4': 1, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12568: Output = NZ  Instr=B10 INC R0; regs={'R4': 1, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12569: Output = NZ  Instr=B10 INC R0; regs={'R4': 1, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12570: Output = NZ  Instr=B10 INC R0; regs={'R4': 1, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12571: Output = NZ  Instr=B10 INC R0; regs={'R4': 1, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12572: Output = NZ  Instr=B10 INC R0; regs={'R4': 1, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12573: Output = NZ  Instr=B10 INC R0; regs={'R4': 1, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12574: Output = NZ  Instr=B10 INC R0; regs={'R4': 1, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12575: Output = NZ  Instr=B10 INC R0; regs={'R4': 1, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12576: Output = NZ  Instr=B10 INC R0; regs={'R4': 1, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12577: Output = NZ  Instr=B10 INC R0; regs={'R4': 1, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12578: Output = NZ  Instr=B10 INC R0; regs={'R4': 1, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12579: Output = NZ  Instr=B10 INC R0; regs={'R4': 1, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12580: Output = NZ  Instr=B10 INC R0; regs={'R4': 1, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12581: Output = NZ  Instr=B10 INC R0; regs={'R4': 1, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 INC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B10 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12582: Output = Z  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12583: Output = NZ  Instr=B12 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12584: Output = Z  Instr=B13 READ T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12585: Output = Z  Instr=B14 RESET T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, 'x011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12586: Output = NZ  Instr=B15 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [0, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12587: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12588: Output = NZ  Instr=B12 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0111101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12589: Output = NZ  Instr=B13 READ T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12590: Output = Z  Instr=B14 RESET T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [1, '0x11101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12591: Output = NZ  Instr=B15 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12592: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12593: Output = NZ  Instr=B12 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12594: Output = NZ  Instr=B13 READ T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '00x1101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12595: Output = NZ  Instr=B14 SET T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [2, '00x1101100000000000'], 'T3': [2, '00x1101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '00x1101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12596: Output = NZ  Instr=B15 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12597: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12598: Output = NZ  Instr=B12 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12599: Output = NZ  Instr=B13 READ T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '001x101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12600: Output = NZ  Instr=B14 SET T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [3, '001x101100000000000'], 'T3': [3, '001x101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '001x101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [3, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12601: Output = NZ  Instr=B15 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [3, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12602: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12603: Output = NZ  Instr=B12 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12604: Output = NZ  Instr=B13 READ T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011x01100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12605: Output = NZ  Instr=B14 SET T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011x01100000000000'], 'T3': [4, '0011x01100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011x01100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [4, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12606: Output = NZ  Instr=B15 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [4, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12607: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12608: Output = NZ  Instr=B12 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12609: Output = Z  Instr=B13 READ T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12610: Output = Z  Instr=B14 RESET T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [5, '00111x1100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '00111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12611: Output = NZ  Instr=B15 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12612: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12613: Output = NZ  Instr=B12 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12614: Output = NZ  Instr=B13 READ T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12615: Output = NZ  Instr=B14 SET T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [6, '001110x100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '001110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12616: Output = NZ  Instr=B15 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12617: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12618: Output = NZ  Instr=B12 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12619: Output = NZ  Instr=B13 READ T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12620: Output = NZ  Instr=B14 SET T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101x00000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 SET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12621: Output = NZ  Instr=B15 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12622: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12623: Output = NZ  Instr=B12 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12624: Output = Z  Instr=B13 READ T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12625: Output = Z  Instr=B14 RESET T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [8, '00111011x0000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '00111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12626: Output = NZ  Instr=B15 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12627: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12628: Output = NZ  Instr=B12 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12629: Output = Z  Instr=B13 READ T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12630: Output = Z  Instr=B14 RESET T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [9, '001110110x000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '001110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12631: Output = NZ  Instr=B15 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12632: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12633: Output = NZ  Instr=B12 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12634: Output = Z  Instr=B13 READ T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12635: Output = Z  Instr=B14 RESET T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100x00000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12636: Output = NZ  Instr=B15 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12637: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12638: Output = NZ  Instr=B12 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12639: Output = Z  Instr=B13 READ T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12640: Output = Z  Instr=B14 RESET T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [11, '00111011000x0000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '00111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12641: Output = NZ  Instr=B15 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12642: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12643: Output = NZ  Instr=B12 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12644: Output = Z  Instr=B13 READ T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12645: Output = Z  Instr=B14 RESET T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [12, '001110110000x000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '001110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12646: Output = NZ  Instr=B15 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12647: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12648: Output = NZ  Instr=B12 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12649: Output = Z  Instr=B13 READ T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12650: Output = Z  Instr=B14 RESET T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000x00000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12651: Output = NZ  Instr=B15 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12652: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12653: Output = NZ  Instr=B12 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12654: Output = Z  Instr=B13 READ T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12655: Output = Z  Instr=B14 RESET T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [14, '00111011000000x0000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '00111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12656: Output = NZ  Instr=B15 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12657: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12658: Output = NZ  Instr=B12 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12659: Output = Z  Instr=B13 READ T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12660: Output = Z  Instr=B14 RESET T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [15, '001110110000000x000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '001110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12661: Output = NZ  Instr=B15 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12662: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12663: Output = NZ  Instr=B12 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12664: Output = Z  Instr=B13 READ T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12665: Output = Z  Instr=B14 RESET T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000x00'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12666: Output = NZ  Instr=B15 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12667: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12668: Output = NZ  Instr=B12 READ T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12669: Output = Z  Instr=B13 READ T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12670: Output = Z  Instr=B14 RESET T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [17, '00111011000000000x0'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 RESET T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '00111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=B14 INC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12671: Output = NZ  Instr=B15 INC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12672: Output = NZ  Instr=B11 TDEC R2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12673: Output = Z  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [18, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12674: Output = NZ  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [17, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12675: Output = NZ  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [16, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12676: Output = NZ  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [15, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12677: Output = NZ  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [14, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12678: Output = NZ  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [13, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12679: Output = NZ  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [12, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12680: Output = NZ  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [11, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12681: Output = NZ  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [10, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12682: Output = NZ  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [9, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12683: Output = NZ  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [8, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12684: Output = NZ  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [7, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12685: Output = NZ  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [6, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12686: Output = NZ  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [5, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12687: Output = NZ  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [4, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12688: Output = NZ  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [3, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12689: Output = NZ  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [2, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12690: Output = NZ  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [1, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12691: Output = NZ  Instr=B16 DEC T2; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12692: Output = Z  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12693: Output = NZ  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12694: Output = NZ  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12695: Output = NZ  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12696: Output = NZ  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12697: Output = NZ  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12698: Output = NZ  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12699: Output = NZ  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12700: Output = NZ  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12701: Output = NZ  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12702: Output = NZ  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12703: Output = NZ  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12704: Output = NZ  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12705: Output = NZ  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12706: Output = NZ  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12707: Output = NZ  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12708: Output = NZ  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12709: Output = NZ  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12710: Output = NZ  Instr=B17 DEC T3; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12711: Output = Z  Instr=ADD NOP; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12712: Output = Z  Instr=C1 TDEC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12713: Output = NZ  Instr=C2 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '0011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12714: Output = Z  Instr=C4 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C4 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12715: Output = Z  Instr=C1 TDEC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12716: Output = Z  Instr=C5 NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12717: Output = Z  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12718: Output = NZ  Instr=C6 INC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C6 TDEC R3; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12719: Output = Z  Instr=C7 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 1, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12720: Output = NZ  Instr=C7 INC R3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 0, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 INC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=C7 TDEC R1; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12721: Output = Z  Instr=MUL NOP; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12722: Output = Z  Instr=D1 TDEC R4; regs={'R4': 1, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12723: Output = NZ  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12724: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12725: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12726: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12727: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12728: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12729: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12730: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12731: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12732: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12733: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12734: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12735: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12736: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12737: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12738: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12739: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12740: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12741: Output = NZ  Instr=D2 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D2 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12742: Output = Z  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12743: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12744: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12745: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12746: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12747: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12748: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12749: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12750: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12751: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12752: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12753: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12754: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12755: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12756: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12757: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12758: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12759: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12760: Output = NZ  Instr=D3 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D3 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12761: Output = Z  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12762: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12763: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, 'x011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '0000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
12764: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, 'x000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
12765: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, 'x000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12766: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12767: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12768: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12769: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1x11101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12770: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [1, '1x00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12771: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [1, '1x00000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [1, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12772: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [2, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12773: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [2, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12774: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [2, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12775: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [2, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '10x1101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [2, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [2, '1000000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
12776: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [2, '10x0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
12777: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [2, '10x0000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [2, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12778: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [3, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12779: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [3, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12780: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [3, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12781: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [3, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '101x101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [3, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [3, '1010000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
12782: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [3, '101x000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
12783: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [3, '101x000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [3, '1011000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12784: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [4, '1011000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12785: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [4, '1011000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12786: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [4, '1011000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12787: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [4, '1011000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1011x01100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [4, '1011000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [4, '1011000000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
12788: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [4, '1011x00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
12789: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [4, '1011x00000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [4, '1011100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12790: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [5, '1011100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12791: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [5, '1011100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12792: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [5, '1011100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12793: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [5, '1011100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '10111x1100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [5, '1011100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12794: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [5, '10111x0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12795: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [5, '10111x0000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [5, '1011100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12796: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [6, '1011100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12797: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [6, '1011100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12798: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [6, '1011100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12799: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [6, '1011100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '101110x100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [6, '1011100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [6, '1011100000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
12800: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [6, '101110x000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
12801: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [6, '101110x000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [6, '1011101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12802: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [7, '1011101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12803: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [7, '1011101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12804: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [7, '1011101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12805: Output = NZ  Instr=D6 SET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [7, '1011101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1011101x00000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 ADD A1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [7, '1011101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [7, '1011101000000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
12806: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [7, '1011101x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '010 bit1', 'MUL': '00000'}; mem={}
12807: Output = NZ  Instr=D8 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [7, '1011101x00000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [7, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12808: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12809: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12810: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12811: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '10111011x0000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12812: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [8, '10111011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12813: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [8, '10111011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12814: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [9, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12815: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [9, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12816: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [9, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12817: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [9, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '101110110x000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [9, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12818: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [9, '101110110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12819: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [9, '101110110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [9, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12820: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [10, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12821: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [10, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12822: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [10, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12823: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [10, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1011101100x00000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [10, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12824: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [10, '1011101100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12825: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [10, '1011101100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [10, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12826: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [11, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12827: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [11, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12828: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [11, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12829: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [11, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '10111011000x0000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [11, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12830: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [11, '10111011000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12831: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [11, '10111011000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [11, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12832: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [12, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12833: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [12, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12834: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [12, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12835: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [12, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '101110110000x000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [12, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12836: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [12, '101110110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12837: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [12, '101110110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [12, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12838: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [13, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12839: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [13, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12840: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [13, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12841: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [13, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1011101100000x00000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [13, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12842: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [13, '1011101100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12843: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [13, '1011101100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [13, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12844: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [14, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12845: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [14, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12846: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [14, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12847: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [14, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '10111011000000x0000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [14, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12848: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [14, '10111011000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12849: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [14, '10111011000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [14, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12850: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [15, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12851: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [15, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12852: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [15, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12853: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [15, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '101110110000000x000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [15, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12854: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [15, '101110110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12855: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [15, '101110110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [15, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12856: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [16, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12857: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [16, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12858: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [16, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12859: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [16, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1011101100000000x00'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [16, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12860: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [16, '1011101100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12861: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [16, '1011101100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [16, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12862: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [17, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12863: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [17, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12864: Output = NZ  Instr=D5 READ T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12865: Output = Z  Instr=D6 RESET T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '10111011000000000x0'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D6 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12866: Output = Z  Instr=D7 ADD B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '10111011000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12867: Output = Z  Instr=D8 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '10111011000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12868: Output = NZ  Instr=D8A INC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12869: Output = NZ  Instr=D4 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12870: Output = Z  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [18, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12871: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [17, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12872: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [16, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12873: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [15, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12874: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [14, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12875: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [13, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12876: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [12, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12877: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [11, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12878: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [10, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12879: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [9, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12880: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [8, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12881: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [7, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12882: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [6, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12883: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [5, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12884: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [4, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12885: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [3, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12886: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [2, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12887: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [1, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12888: Output = NZ  Instr=D9 DEC T3; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12889: Output = Z  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12890: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12891: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [16, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12892: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [15, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12893: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [14, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12894: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [13, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12895: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [12, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12896: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [11, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12897: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [10, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12898: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [9, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12899: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12900: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [7, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12901: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [6, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12902: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [5, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12903: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [4, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12904: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [3, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12905: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [2, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12906: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [1, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12907: Output = NZ  Instr=D10 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12908: Output = Z  Instr=D1 TDEC R4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12909: Output = Z  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12910: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12911: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12912: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12913: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12914: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12915: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12916: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12917: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12918: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12919: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12920: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12921: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12922: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12923: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12924: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12925: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12926: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12927: Output = NZ  Instr=D11 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D11 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12928: Output = Z  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12929: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12930: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12931: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12932: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12933: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12934: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12935: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12936: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12937: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12938: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12939: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12940: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12941: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12942: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12943: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12944: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12945: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12946: Output = NZ  Instr=D12 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=D12 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12947: Output = Z  Instr=COMP NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12948: Output = Z  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12949: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12950: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12951: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [1, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12952: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [1, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12953: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [1, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12954: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [2, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12955: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [2, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12956: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [2, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12957: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [3, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12958: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [3, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12959: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [3, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12960: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 14, 'R3': 1, 'T4': [4, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12961: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [4, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12962: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [4, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12963: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 13, 'R3': 1, 'T4': [5, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12964: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [5, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12965: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [5, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12966: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 12, 'R3': 1, 'T4': [6, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12967: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [6, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12968: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [6, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12969: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 11, 'R3': 1, 'T4': [7, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12970: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [7, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12971: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [7, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12972: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 10, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12973: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12974: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12975: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 9, 'R3': 1, 'T4': [9, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12976: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [9, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12977: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [9, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12978: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 8, 'R3': 1, 'T4': [10, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12979: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [10, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12980: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [10, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12981: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 7, 'R3': 1, 'T4': [11, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12982: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [11, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12983: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [11, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12984: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 6, 'R3': 1, 'T4': [12, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12985: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [12, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12986: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [12, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12987: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 5, 'R3': 1, 'T4': [13, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12988: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [13, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12989: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [13, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12990: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 4, 'R3': 1, 'T4': [14, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12991: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [14, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12992: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [14, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12993: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 3, 'R3': 1, 'T4': [15, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12994: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [15, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12995: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [15, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12996: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 2, 'R3': 1, 'T4': [16, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12997: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [16, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12998: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [16, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
12999: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 1, 'R3': 1, 'T4': [17, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13000: Output = NZ  Instr=E2 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13001: Output = NZ  Instr=E3 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13002: Output = NZ  Instr=E1 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13003: Output = Z  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13004: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '000010011000000000x'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13005: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '101110110000000000x'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [18, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13006: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [18, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13007: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13008: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '00001001100000000x0'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13009: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '10111011000000000x0'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [17, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13010: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [16, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [17, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13011: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [16, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13012: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [16, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000x00'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [16, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13013: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [16, '1011101100000000x00'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [16, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13014: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [15, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [16, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13015: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [15, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13016: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [15, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '000010011000000x000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [15, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13017: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [15, '101110110000000x000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [15, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13018: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [14, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [15, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13019: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [14, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13020: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [14, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '00001001100000x0000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [14, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13021: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [14, '10111011000000x0000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [14, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13022: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [13, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [14, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13023: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [13, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13024: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [13, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000x00000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [13, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13025: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [13, '1011101100000x00000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [13, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13026: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [12, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [13, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13027: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [12, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13028: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [12, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '000010011000x000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [12, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13029: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [12, '101110110000x000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [12, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13030: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [11, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [12, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13031: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [11, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13032: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [11, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '00001001100x0000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [11, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13033: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [11, '10111011000x0000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [11, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13034: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [10, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [11, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13035: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [10, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13036: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [10, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110x00000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [10, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13037: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [10, '1011101100x00000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [10, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13038: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [9, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [10, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13039: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [9, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13040: Output = Z  Instr=E5 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [9, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '000010011x000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [9, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13041: Output = Z  Instr=E6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [9, '101110110x000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E6 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [9, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13042: Output = NZ  Instr=E7 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [9, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13043: Output = NZ  Instr=E4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13044: Output = NZ  Instr=E8 SET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '00001001x0000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E8 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13045: Output = Z  Instr=E12 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [8, '10111011x0000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=E12 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [8, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13046: Output = NZ  Instr=E12 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [7, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13047: Output = NZ  Instr=E12 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [6, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13048: Output = NZ  Instr=E12 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [5, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13049: Output = NZ  Instr=E12 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [4, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13050: Output = NZ  Instr=E12 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [3, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13051: Output = NZ  Instr=E12 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13052: Output = NZ  Instr=E12 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13053: Output = NZ  Instr=E12 DEC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13054: Output = Z  Instr=E13 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [8, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13055: Output = NZ  Instr=E13 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [7, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13056: Output = NZ  Instr=E13 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [6, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13057: Output = NZ  Instr=E13 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [5, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13058: Output = NZ  Instr=E13 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [4, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13059: Output = NZ  Instr=E13 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [3, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13060: Output = NZ  Instr=E13 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [2, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13061: Output = NZ  Instr=E13 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [1, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13062: Output = NZ  Instr=E13 DEC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13063: Output = Z  Instr=SUB NOP; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13064: Output = Z  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13065: Output = NZ  Instr=F1 INC R1; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13066: Output = NZ  Instr=F1 INC R1; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13067: Output = NZ  Instr=F1 INC R1; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13068: Output = NZ  Instr=F1 INC R1; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13069: Output = NZ  Instr=F1 INC R1; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13070: Output = NZ  Instr=F1 INC R1; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13071: Output = NZ  Instr=F1 INC R1; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13072: Output = NZ  Instr=F1 INC R1; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13073: Output = NZ  Instr=F1 INC R1; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13074: Output = NZ  Instr=F1 INC R1; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13075: Output = NZ  Instr=F1 INC R1; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13076: Output = NZ  Instr=F1 INC R1; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13077: Output = NZ  Instr=F1 INC R1; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13078: Output = NZ  Instr=F1 INC R1; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13079: Output = NZ  Instr=F1 INC R1; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13080: Output = NZ  Instr=F1 INC R1; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13081: Output = NZ  Instr=F1 INC R1; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13082: Output = NZ  Instr=F1 INC R1; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F1 TDEC R0; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13083: Output = Z  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 0, 'R1': 18, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13084: Output = NZ  Instr=F2 INC R0; regs={'R4': 0, 'R0': 0, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 INC R2; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 0, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 1, 'R1': 17, 'R2': 1, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13085: Output = NZ  Instr=F2 INC R0; regs={'R4': 0, 'R0': 1, 'R1': 16, 'R2': 1, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 INC R2; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 1, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 2, 'R1': 16, 'R2': 2, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13086: Output = NZ  Instr=F2 INC R0; regs={'R4': 0, 'R0': 2, 'R1': 15, 'R2': 2, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 INC R2; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 2, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 3, 'R1': 15, 'R2': 3, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13087: Output = NZ  Instr=F2 INC R0; regs={'R4': 0, 'R0': 3, 'R1': 14, 'R2': 3, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 INC R2; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 3, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 4, 'R1': 14, 'R2': 4, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13088: Output = NZ  Instr=F2 INC R0; regs={'R4': 0, 'R0': 4, 'R1': 13, 'R2': 4, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 INC R2; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 4, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 5, 'R1': 13, 'R2': 5, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13089: Output = NZ  Instr=F2 INC R0; regs={'R4': 0, 'R0': 5, 'R1': 12, 'R2': 5, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 INC R2; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 5, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 6, 'R1': 12, 'R2': 6, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13090: Output = NZ  Instr=F2 INC R0; regs={'R4': 0, 'R0': 6, 'R1': 11, 'R2': 6, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 INC R2; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 6, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 7, 'R1': 11, 'R2': 7, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13091: Output = NZ  Instr=F2 INC R0; regs={'R4': 0, 'R0': 7, 'R1': 10, 'R2': 7, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 INC R2; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 7, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 8, 'R1': 10, 'R2': 8, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13092: Output = NZ  Instr=F2 INC R0; regs={'R4': 0, 'R0': 8, 'R1': 9, 'R2': 8, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 INC R2; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 8, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 9, 'R1': 9, 'R2': 9, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13093: Output = NZ  Instr=F2 INC R0; regs={'R4': 0, 'R0': 9, 'R1': 8, 'R2': 9, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 INC R2; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 9, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 10, 'R1': 8, 'R2': 10, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13094: Output = NZ  Instr=F2 INC R0; regs={'R4': 0, 'R0': 10, 'R1': 7, 'R2': 10, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 INC R2; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 10, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 11, 'R1': 7, 'R2': 11, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13095: Output = NZ  Instr=F2 INC R0; regs={'R4': 0, 'R0': 11, 'R1': 6, 'R2': 11, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 INC R2; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 11, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 12, 'R1': 6, 'R2': 12, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13096: Output = NZ  Instr=F2 INC R0; regs={'R4': 0, 'R0': 12, 'R1': 5, 'R2': 12, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 INC R2; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 12, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 13, 'R1': 5, 'R2': 13, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13097: Output = NZ  Instr=F2 INC R0; regs={'R4': 0, 'R0': 13, 'R1': 4, 'R2': 13, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 INC R2; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 13, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 14, 'R1': 4, 'R2': 14, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13098: Output = NZ  Instr=F2 INC R0; regs={'R4': 0, 'R0': 14, 'R1': 3, 'R2': 14, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 INC R2; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 14, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 15, 'R1': 3, 'R2': 15, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13099: Output = NZ  Instr=F2 INC R0; regs={'R4': 0, 'R0': 15, 'R1': 2, 'R2': 15, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 INC R2; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 15, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 16, 'R1': 2, 'R2': 16, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13100: Output = NZ  Instr=F2 INC R0; regs={'R4': 0, 'R0': 16, 'R1': 1, 'R2': 16, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 INC R2; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 16, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 17, 'R1': 1, 'R2': 17, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13101: Output = NZ  Instr=F2 INC R0; regs={'R4': 0, 'R0': 17, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 INC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F2 TDEC R1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13102: Output = Z  Instr=F3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 18, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13103: Output = NZ  Instr=F4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '0000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13104: Output = Z  Instr=F5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, 'x000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13105: Output = NZ  Instr=F6 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, 'x011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, 'x000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}  Instr=F6 SUB B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, 'x000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000'}; mem={}
13106: Output = NZ  Instr=F7 SET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, 'x000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000', 'SUB': '100 stopper0 bit1'}; mem={}  Instr=F7 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [0, '1000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000', 'SUB': '100 stopper0 bit1'}; mem={}
13107: Output = NZ  Instr=F8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [0, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '1000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000', 'SUB': '100 stopper0 bit1'}; mem={}
13108: Output = NZ  Instr=F3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 17, 'R3': 1, 'T4': [1, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '1000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000', 'SUB': '100 stopper0 bit1'}; mem={}
13109: Output = NZ  Instr=F4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [1, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '1000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000', 'SUB': '100 stopper0 bit1'}; mem={}
13110: Output = Z  Instr=F5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [1, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '1x00100110000000000'], 'ADD': '000 bit0', 'MUL': '00000', 'SUB': '100 stopper0 bit1'}; mem={}
13111: Output = Z  Instr=F6 RESET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [1, '1x11101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '1x00100110000000000'], 'ADD': '000 bit0', 'MUL': '00000', 'SUB': '100 stopper0 bit1'}; mem={}  Instr=F6 SUB B1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [1, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '1x00100110000000000'], 'ADD': '000 bit0', 'MUL': '00000', 'SUB': '100 stopper0 bit1'}; mem={}
Discrepancy found at instruction 13112: output is NZ in the real pattern.
13112: Output = Z  Instr=F7 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [1, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '1x00100110000000000'], 'ADD': '000 bit0', 'MUL': '00000', 'SUB': '100 stopper0 bit1'}; mem={}  Instr=F7 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [1, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [1, '1000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000', 'SUB': '100 stopper0 bit1'}; mem={}
Discrepancy found in T1 bit #1 at (-36084, 58347) at instruction 13113: emulator says it's a 0.
13113: Output = NZ  Instr=F8 INC T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [1, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '1000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000', 'SUB': '100 stopper0 bit1'}; mem={}
Discrepancy found in T1 bit #1 at (-36084, 58347) at instruction 13114: emulator says it's a 0.
13114: Output = NZ  Instr=F3 TDEC R2; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 16, 'R3': 1, 'T4': [2, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '1000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000', 'SUB': '100 stopper0 bit1'}; mem={}
Discrepancy found in T1 bit #1 at (-36084, 58347) at instruction 13115: emulator says it's a 0.
13115: Output = NZ  Instr=F4 READ T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [2, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '1000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000', 'SUB': '100 stopper0 bit1'}; mem={}
Discrepancy found in T1 bit #1 at (-36084, 58347) at instruction 13116: emulator says it's a 0.
13116: Output = Z  Instr=F5 READ T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [2, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '10x0100110000000000'], 'ADD': '000 bit0', 'MUL': '00000', 'SUB': '100 stopper0 bit1'}; mem={}
Discrepancy found in T1 bit #1 at (-36084, 58347) at instruction 13117: emulator says it's a 0.
13117: Output = NZ  Instr=F6 SET T4; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [2, '10x1101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '10x0100110000000000'], 'ADD': '000 bit0', 'MUL': '00000', 'SUB': '100 stopper0 bit1'}; mem={}  Instr=F6 SUB B0; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [2, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '10x0100110000000000'], 'ADD': '000 bit0', 'MUL': '00000', 'SUB': '100 stopper0 bit1'}; mem={}
Discrepancy found in T1 bit #1 at (-36084, 58347) at instruction 13118: emulator says it's a 0.
13118: Output = Z  Instr=F7 RESET T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [2, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '10x0100110000000000'], 'ADD': '000 bit0', 'MUL': '00000', 'SUB': '100 stopper0 bit1'}; mem={}  Instr=F7 INC T1; regs={'R4': 0, 'R0': 18, 'R1': 0, 'R2': 15, 'R3': 1, 'T4': [2, '1011101100000000000'], 'T2': [0, '0011101100000000000'], 'T3': [0, '1011101100000000000'], 'T0': [0, '0110100000000000000'], 'T1': [2, '1000100110000000000'], 'ADD': '000 bit0', 'MUL': '00000', 'SUB': '100 stopper0 bit1'}; mem={}
Discrepancy found in T1 bit #1 at (-36084, 58347) at instruction 13119: emulator says it's a 0.
13119: Output = NZ